Issued Patents All Time
Showing 26–50 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10606592 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-03-31 |
| 10606591 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-03-31 |
| 10606590 | Effective address based load store unit in out of order processors | Bryan Lloyd | 2020-03-31 |
| 10606593 | Effective address based load store unit in out of order processors | Bryan Lloyd | 2020-03-31 |
| 10579387 | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor | Christopher Gonzalez, Bryan Lloyd | 2020-03-03 |
| 10579384 | Effective address based instruction fetch unit for out of order processors | Robert Alan Philhower | 2020-03-03 |
| 10572257 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-02-25 |
| 10572264 | Completing coalesced global completion table entries in an out-of-order processor | Joel A. Silberman | 2020-02-25 |
| 10572256 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-02-25 |
| 10564979 | Coalescing global completion table entries in an out-of-order processor | Joel A. Silberman | 2020-02-18 |
| 10564976 | Scalable dependency matrix with multiple summary bits in an out-of-order processor | Joel A. Silberman | 2020-02-18 |
| 10534616 | Load-hit-load detection in an out-of-order processor | Christopher Gonzalez, Bryan Lloyd | 2020-01-14 |
| 10481915 | Split store data queue design for an out-of-order processor | Bryan Lloyd | 2019-11-19 |
| 10417002 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Bryan Lloyd, Shih-Hsiung S. Tung | 2019-09-17 |
| 10394558 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Bryan Lloyd | 2019-08-27 |
| 10387162 | Effective address table with multiple taken branch handling for out-of-order processors | Richard J. Eickemeyer | 2019-08-20 |
| 10324856 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Bryan Lloyd, Shih-Hsiung S. Tung | 2019-06-18 |
| 10310988 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Bryan Lloyd, Shih-Hsiung S. Tung | 2019-06-04 |
| 10095524 | Method and apparatus for dynamically replacing legacy instructions with a single executable instruction utilizing a wide datapath | Michael K. Gschwind | 2018-10-09 |
| 10019370 | Probabilistic associative cache | Bulent Abali, John Steven Dodson, Moinuddin K. Qureshi | 2018-07-10 |
| 9971704 | Data compression accelerator methods, apparatus and design structure with improved resource utilization | Bulent Abali, Bartholomew Blaner | 2018-05-15 |
| 9910781 | Page table including data fetch width indicator | Michael K. Gschwind, Jose E. Moreira | 2018-03-06 |
| 9524100 | Page table including data fetch width indicator | Michael K. Gschwind, Jose E. Moreira | 2016-12-20 |
| 9513805 | Page table including data fetch width indicator | Michael K. Gschwind, Jose E. Moreira | 2016-12-06 |
| 9489207 | Processor and method for partially flushing a dispatched instruction group including a mispredicted branch | William E. Burky, Brian R. Mestan, Dung Q. Nguyen, Benjamin W. Stolt | 2016-11-08 |