BS

Balaram Sinharoy

IBM: 187 patents #187 of 70,183Top 1%
Google: 1 patents #14,769 of 22,993Top 65%
📍 Cupertino, CA: #27 of 6,989 inventorsTop 1%
🗺 California: #634 of 386,348 inventorsTop 1%
Overall (All Time): #3,845 of 4,157,543Top 1%
188
Patents All Time

Issued Patents All Time

Showing 76–100 of 188 patents

Patent #TitleCo-InventorsDate
8359589 Helper thread for pre-fetching data Ravi Kumar Arimilli, Juan C. Rubio 2013-01-22
8356151 Reporting of partially performed memory move Ravi Kumar Arimilli, Robert S. Blackmore, Ronald Nick Kalla, Chulho Kim, Hanhong Xue 2013-01-15
8347068 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen 2013-01-01
8327345 Computation table for block computation Ravi Kumar Arimilli 2012-12-04
8327101 Cache management during asynchronous memory move operations Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue 2012-12-04
8285971 Block driven computation with an address generation accelerator Ravi Kumar Arimilli 2012-10-09
8281106 Specifying an addressing relationship in an operand data structure Ravi Kumar Arimilli 2012-10-02
8275963 Asynchronous memory move across physical nodes with dual-sided communication Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue 2012-09-25
8266381 Varying an amount of data retrieved from memory based upon an instruction hint Ravi Kumar Arimilli, Gheorghe C. Cascaval, William E. Speight, Lixin Zhang 2012-09-11
8255591 Method and system for managing cache injection in a multiprocessor system Patrick J. Bohrer, Ahmed Gheith, Peter Hochschild, Ramakrishnan Rajamony, Hazim Shafi 2012-08-28
8250307 Sourcing differing amounts of prefetch data in response to data prefetch requests Ravi Kumar Arimilli, Gheorghe C. Cascaval, William E. Speight, Lixin Zhang 2012-08-21
8245004 Mechanisms for communicating with an asynchronous memory mover to perform AMM operations Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue 2012-08-14
8230422 Assist thread for injecting cache memory in a microprocessor Patrick J. Bohrer, Orran Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi +1 more 2012-07-24
8209698 Processor core with per-thread resource usage accounting logic William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Larry Scott Leitner 2012-06-26
8209488 Techniques for prediction-based indirect data prefetching Ravi Kumar Arimilli, William E. Speight, Lixin Zhang 2012-06-26
8176254 Specifying an access hint for prefetching limited use data in a cache hierarchy Bradly G. Frey, Guy L. Guthrie, Cathy May, Peter K. Szwed 2012-05-08
8166277 Data prefetching using indirect addressing Ravi Kumar Arimilli, William E. Speight, Lixin Zhang 2012-04-24
8161264 Techniques for data prefetching using indirect addressing with offset Ravi Kumar Arimilli, William E. Speight, Lixin Zhang 2012-04-17
8161265 Techniques for multi-level indirect data prefetching Ravi Kumar Arimilli, William E. Speight, Lixin Zhang 2012-04-17
8161263 Techniques for indirect data prefetching Ravi Kumar Arimilli, William E. Speight, Lixin Zhang 2012-04-17
8145885 Apparatus for randomizing instruction thread interleaving in a multi-thread processor Ronald Nick Kalla, Minh Michelle Quy Pham, John W. Ward, III 2012-03-27
8140801 Efficient and flexible memory copy operation Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma 2012-03-20
8140764 System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory Xiaowei Shen, Robert B. Tremaine, Robert W. Wisniewski 2012-03-20
8140759 Specifying an access hint for prefetching partial cache block data in a cache hierarchy Bradly G. Frey, Guy L. Guthrie, Cathy May, Ramakrishnan Rajamony, William J. Starke +1 more 2012-03-20
8131976 Tracking effective addresses in an out-of-order processor Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan +3 more 2012-03-06