Issued Patents All Time
Showing 101–125 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8127115 | Group formation with multiple taken branches per group | Richard W. Doing, Kevin Neal Magil, Jeffrey R. Summers, James Albert Van Norstrand, Jr. | 2012-02-28 |
| 8095758 | Fully asynchronous memory mover | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2012-01-10 |
| 8086826 | Dependency tracking for enabling successive processor instructions to issue | Mary D. Brown, William E. Burky, Dung Q. Nguyen | 2011-12-27 |
| 8041928 | Information handling system with real and virtual load/store instruction issue queue | William E. Burky, Kurt A. Feiste, Dung Q. Nguyen, Albert Thomas Williams | 2011-10-18 |
| 8015380 | Launching multiple concurrent memory moves via a fully asynchronoous memory mover | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-09-06 |
| 7996564 | Remote asynchronous data mover | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ronald Nick Kalla, Ramakrishnan Rajamony, William E. Speight +1 more | 2011-08-09 |
| 7991981 | Completion of asynchronous memory move in the presence of a barrier operation | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-08-02 |
| 7958327 | Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-06-07 |
| 7949859 | Mechanism for avoiding check stops in speculative accesses while operating in real mode | Ronald Nick Kalla, Cathy May, Edward John Silha, Shih-Hsiung S. Tung | 2011-05-24 |
| 7941627 | Specialized memory move barrier operations | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-05-10 |
| 7937570 | Termination of in-flight asynchronous memory move | Ravi Kumar Arimilli, Robert S. Blackmore, Ronald Nick Kalla, Chulho Kim, Hanhong Xue | 2011-05-03 |
| 7934061 | Methods and arrangements to manage on-chip memory to reduce memory latency | Dilma M. Da Silva, Elmootazbellah Nabil Elnozahy, Orran Krieger, Hazim Shafi, Xiaowei Shen +1 more | 2011-04-26 |
| 7930504 | Handling of address conflicts during asynchronous memory move operations | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-04-19 |
| 7921275 | Method for enabling direct prefetching of data during asychronous memory move operation | Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2011-04-05 |
| 7913041 | Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint | Xiaowei Shen, Robert B. Tremaine, Robert W. Wisniewski | 2011-03-22 |
| 7904657 | Cache residence prediction | Xiaowei Shen, Jaehyuk Huh | 2011-03-08 |
| 7890703 | Cache injection using semi-synchronous memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2011-02-15 |
| 7882321 | Validity of address ranges used in semi-synchronous memory copy operations | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2011-02-01 |
| 7870406 | Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor | Richard Louis Arndt, Scott Barnett Swaney, Kenneth L. Ward | 2011-01-11 |
| 7844778 | Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements | Xiaowei Shen, Robert W. Wisniewski | 2010-11-30 |
| 7827388 | Apparatus for adjusting instruction thread priority in a multi-thread processor | John W. Ward, III, Minh Michelle Quy Pham, Ronald Nick Kalla | 2010-11-02 |
| 7809929 | Universal register rename mechanism for instructions with multiple targets in a microprocessor | Hung Q. Le, Dung Q. Nguyen | 2010-10-05 |
| 7779232 | Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches | Richard W. Doing, Michael O. Klett, Kevin N. Magill, Brian R. Mestan, David Mui +1 more | 2010-08-17 |
| 7774654 | Method and apparatus for preventing soft error accumulation in register arrays | Pradip Bose, Jude A. Rivers, Victor Zyuban | 2010-08-10 |
| 7765384 | Universal register rename mechanism for targets of different instruction types in a microprocessor | Hung Q. Le, Dung Q. Nguyen | 2010-07-27 |