Issued Patents All Time
Showing 151–175 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7266642 | Cache residence prediction | Xiaowei Shen, Jaehyuk Huh | 2007-09-04 |
| 7254678 | Enhanced STCX design to improve subsequent load efficiency | Gregory W. Alexander, Juan Jose Arevalo, Shih-Hsiung S. Tung | 2007-08-07 |
| 7228388 | Enabling and disabling cache bypass using predicted cache line usage | Zhigang Hu, John T. Robinson, Xiaowei Shen | 2007-06-05 |
| 7213135 | Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions | William E. Burky, Ronald Nick Kalla, John W. Ward, III | 2007-05-01 |
| 7194587 | Localized cache block flush instruction | John McCalpin, Dereck Edward Williams, Kenneth L. Wright | 2007-03-20 |
| 7155600 | Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor | William E. Burky, Michael Stephen Floyd, Ronald Nick Kalla | 2006-12-26 |
| 7143267 | Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor | Eric Jason Fluhr, Cathy May | 2006-11-28 |
| 7120784 | Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment | Gregory W. Alexander, Scott Bruce Frommer, David S. Levitan | 2006-10-10 |
| 7093111 | Recovery of global history vector in the event of a non-branch flush | Scott Bruce Frommer | 2006-08-15 |
| 7051221 | Performance throttling for temperature reduction in a microprocessor | Joachim Clabes, Michael Stephen Floyd, Ronald Nick Kalla | 2006-05-23 |
| 7039768 | Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions | Gregory W. Alexander, David S. Levitan | 2006-05-02 |
| 7032097 | Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache | Gregory W. Alexander, David S. Levitan, William J. Starke | 2006-04-18 |
| 7000096 | Branch prediction circuits and methods and systems using the same | — | 2006-02-14 |
| 7000233 | Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread | David S. Levitan | 2006-02-14 |
| 6981128 | Atomic quad word storage in a simultaneous multithreaded system | Eric Jason Fluhr, Joaquin Hinojosa, Ronald Nick Kalla, Bruce Joseph Ronchetti | 2005-12-27 |
| 6976157 | Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables | — | 2005-12-13 |
| 6971000 | Use of software hint for branch prediction in the absence of hint bit in the branch instruction | Steven Wayne White | 2005-11-29 |
| 6961875 | Method and apparatus for capturing event traces for debug and analysis | Michael Stephen Floyd | 2005-11-01 |
| 6910124 | Apparatus and method for recovering a link stack from mis-speculation | — | 2005-06-21 |
| 6879928 | Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control | Joachim Clabes, Lawrence Powell, Daniel Stasiak, Michael Fan Wang, Michael Stephen Floyd | 2005-04-12 |
| 6877089 | Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program | — | 2005-04-05 |
| 6848044 | Circuits and methods for recovering link stack data upon branch instruction mis-speculation | Lee Evan Eisen, James Allan Kahle, William J. Starke | 2005-01-25 |
| 6823446 | Apparatus and method for performing branch predictions using dual branch history tables and for updating such branch history tables | — | 2004-11-23 |
| 6823447 | Software hint to improve the branch target prediction accuracy | Robert William Hay | 2004-11-23 |
| 6766441 | Prefetching instructions in mis-predicted path for low confidence branches | — | 2004-07-20 |