Issued Patents All Time
Showing 126–150 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7725682 | Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit | Michael K. Gschwind | 2010-05-25 |
| 7707396 | Data processing system, processor and method of data processing having improved branch target address cache | Jeffrey Powers Bradford, Richard W. Doing, Richard J. Eickemeyer, Wael R. El-Essawy, Douglas R. G. Logan +2 more | 2010-04-27 |
| 7676637 | Location-aware cache-to-cache transfers | Xiaowei Shen, Jaehyuk Huh | 2010-03-09 |
| 7660971 | Method and system for dependency tracking and flush recovery for an out-of-order microprocessor | Vikas Agarwal, William E. Burky, Krishnan K. Kailas | 2010-02-09 |
| 7657893 | Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor | William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Larry Scott Leitner | 2010-02-02 |
| 7634642 | Mechanism to save and restore cache and translation trace for fast context switch | Peter Hochschild, Xiaowei Shen, Robert W. Wisniewski | 2009-12-15 |
| 7631308 | Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors | James Wilson Bishop, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto, Raymond Cheung Yeung | 2009-12-08 |
| 7574562 | Latency-aware thread scheduling in non-uniform cache architecture systems | Xiaowei Shen, Robert W. Wisniewski | 2009-08-11 |
| 7523260 | Propagating data using mirrored lock caches | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2009-04-21 |
| 7506132 | Validity of address ranges used in semi-synchronous memory copy operations | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2009-03-17 |
| 7506139 | Method and apparatus for register renaming using multiple physical register files and avoiding associative search | William E. Burky, Krishnan K. Kailas | 2009-03-17 |
| 7496915 | Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes | William J. Armstrong, Bruce Mealey, Naresh Nayar | 2009-02-24 |
| 7493523 | Method and apparatus for preventing soft error accumulation in register arrays | Pradip Bose, Jude A. Rivers, Victor Zyuban | 2009-02-17 |
| 7484062 | Cache injection semi-synchronous memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2009-01-27 |
| 7469407 | Method for resource balancing using dispatch flush in a simultaneous multithread processor | William E. Burky, Richard J. Eickemeyer, Ronald Nick Kalla, David S. Levitan, John W. Ward, III | 2008-12-23 |
| 7467280 | Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache | Xiaowei Shen, Robert B. Tremaine, Robert W. Wisniewski | 2008-12-16 |
| 7454585 | Efficient and flexible memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma | 2008-11-18 |
| 7437517 | Methods and arrangements to manage on-chip memory to reduce memory latency | Dilma M. Da Silva, Elmootazbellah Nabil Elnozahy, Orran Krieger, Hazim Shafi, Xiaowei Shen +1 more | 2008-10-14 |
| 7401208 | Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor | Ronald Nick Kalla, Minh Michelle Quy Pham, John W. Ward, III | 2008-07-15 |
| 7401207 | Apparatus and method for adjusting instruction thread priority in a multi-thread processor | Ronald Nick Kalla, Minh Michelle Quy Pham, John W. Ward, III | 2008-07-15 |
| 7392366 | Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches | Pradip Bose, Alper Buyuktosunoglu, Richard J. Eickemeyer, Lee Evan Eisen, Philip G. Emma +4 more | 2008-06-24 |
| 7370177 | Mechanism for avoiding check stops in speculative accesses while operating in real mode | Ronald Nick Kalla, Cathy May, Edward John Silha, Shih-Hsiung S. Tung | 2008-05-06 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor | William E. Burky, Ronald Nick Kalla, David A. Schroter | 2008-04-22 |
| 7360062 | Method and apparatus for selecting an instruction thread for processing in a multi-thread processor | Ronald Nick Kalla, Minh Michelle Quy Pham, John W. Ward, III | 2008-04-15 |
| 7287122 | Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing | Ramakrishnan Rajamony, Xiaowei Shen | 2007-10-23 |