BS

Balaram Sinharoy

IBM: 187 patents #187 of 70,183Top 1%
Google: 1 patents #14,769 of 22,993Top 65%
📍 Cupertino, CA: #27 of 6,989 inventorsTop 1%
🗺 California: #634 of 386,348 inventorsTop 1%
Overall (All Time): #3,845 of 4,157,543Top 1%
188
Patents All Time

Issued Patents All Time

Showing 176–188 of 188 patents

Patent #TitleCo-InventorsDate
6766443 Compression of execution path history to improve branch prediction accuracy 2004-07-20
6760867 Guaranteed method and apparatus for capture of debug data Michael Stephen Floyd 2004-07-06
6745323 Global history vector recovery circuits and methods and systems using the same 2004-06-01
6721874 Method and system for dynamically shared completion table supporting multiple threads in a processing system Hung Q. Le, Peichun Peter Liu 2004-04-13
6662360 Method and system for software control of hardware branch prediction mechanism in a data processor Robert William Hay, James Allan Kahle, Brian R. Konigsburg, David S. Levitan 2003-12-09
6651162 Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache David S. Levitan, Shashank Nemawarkar, William J. Starke 2003-11-18
6633974 Apparatus and method for controlling link stack corruption during speculative instruction branching using multiple stacks 2003-10-14
6598152 Increasing the overall prediction accuracy for multi-cycle branch prediction and apparatus by enabling quick recovery 2003-07-22
6526503 Apparatus and method for accessing a memory device during speculative instruction branching 2003-02-25
6484256 Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table David S. Levitan 2002-11-19
6457120 Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions 2002-09-24
6449714 Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution 2002-09-10
6247097 Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions 2001-06-12