Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11704158 | Managing processing system efficiency | Liqun Cheng, Haishan ZHU, David Lo, Parthasarathy Ranganathan, Nishant Patil | 2023-07-18 |
| 10908964 | Managing processing system efficiency | Liqun Cheng, Haishan ZHU, David Lo, Parthasarathy Ranganathan, Nishant Patil | 2021-02-02 |
| 10884928 | Data caching | Richard M. Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan | 2021-01-05 |
| 10481811 | Asynchronous copying of data within memory | Liqun Cheng, Parthasarathy Ranganathan, Michael Marty, Andrew Gallatin | 2019-11-19 |
| 10303604 | Data caching | Richard M. Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan | 2019-05-28 |
| 10218779 | Machine level resource distribution | Liqun Cheng, Parthasarathy Ranganathan | 2019-02-26 |
| 10216636 | Controlled cache injection of incoming data | Liqun Cheng, Parthasarathy Ranganathan | 2019-02-26 |
| 10191672 | Asynchronous copying of data within memory | Liqun Cheng, Parthasarathy Ranganathan, Michael Marty, Andrew Gallatin | 2019-01-29 |
| 10073817 | Optimized matrix multiplication using vector multiplication of interleaved matrix values | Nishant Patil, Matthew Jeremy Sarett, Benoit Steiner, Vincent O. Vanhoucke | 2018-09-11 |
| 10055350 | Controlled cache injection of incoming data | Liqun Cheng, Parthasarathy Ranganathan | 2018-08-21 |
| 9830303 | Optimized matrix multiplication using vector multiplication of interleaved matrix values | Nishant Patil, Matthew Jeremy Sarett, Benoit Steiner, Vincent O. Vanhoucke | 2017-11-28 |
| 9645974 | Optimized matrix multiplication using vector multiplication of interleaved matrix values | Nishant Patil, Matthew Jeremy Sarett, Benoit Steiner, Vincent O. Vanhoucke | 2017-05-09 |
| 9600417 | Data caching | Richard M. Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan | 2017-03-21 |
| 9594687 | Virtualization-aware prefetching | Richard M. Yoo, Liqun Cheng, Parthasarathy Ranganathan | 2017-03-14 |
| 9436258 | Dynamic service level objective power control in distributed process | David Lo, Liqun Cheng | 2016-09-06 |
| 8605578 | System and method for handling of destination host side congestion | Peter Hochschild, Rajeev Sivaram, Sridhar Raman | 2013-12-10 |
| 8364849 | Snapshot interface operations | Piyush Chaudhary, Jason E. Goscinski, Leonard W. Helmer, Jr., Peter Hochschild, Deryck X. Hong +4 more | 2013-01-29 |
| 8140801 | Efficient and flexible memory copy operation | Ravi Kumar Arimilli, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2012-03-20 |
| 8056087 | Effective use of a hardware barrier synchronization register for protocol synchronization | Piyush Chaudhary, Chulho Kim, Rajeev Sivaram, Hanhong Xue | 2011-11-08 |
| 8031639 | Efficient probabilistic duplicate packet detector in computer networks | Carl A. Bender, Fu Chung Chang, Kevin J. Gildea, Jay R. Herring, Peter Hochschild +1 more | 2011-10-04 |
| 8023417 | Failover mechanisms in RDMA operations | Robert S. Blackmore, Fu Chung Chang, Piyush Chaudhary, Jason E. Goscinski, Leonard W. Helmer, Jr. +4 more | 2011-09-20 |
| 7996593 | Interrupt handling using simultaneous multi-threading | Robert S. Blackmore, Peter Hochschild | 2011-08-09 |
| 7987467 | Scale across in a grid computing environment | Waiman Chan, Joseph F. Skovira | 2011-07-26 |
| 7890703 | Cache injection using semi-synchronous memory copy operation | Ravi Kumar Arimilli, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-15 |
| 7882321 | Validity of address ranges used in semi-synchronous memory copy operations | Ravi Kumar Arimilli, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-01 |