Issued Patents All Time
Showing 26–50 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10241972 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Jintao Zhang | 2019-03-26 |
| 10120685 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Sunil K. Shukla | 2018-11-06 |
| 10007523 | Predicting cache misses using data access behavior and instruction address | Brian R. Prasky | 2018-06-26 |
| 9804967 | Methods of cache preloading on a partition or a context switch | Harold W. Cain, III, Jason D. Zebchuk | 2017-10-31 |
| 9766937 | Thread-based cache content saving for task switching | Harold W. Cain, III, David M. Daly, Brian R. Prasky | 2017-09-19 |
| 9760489 | Private memory table for reduced memory coherence traffic | David M. Daly | 2017-09-12 |
| 9760490 | Private memory table for reduced memory coherence traffic | David M. Daly | 2017-09-12 |
| 9740497 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2017-08-22 |
| 9740496 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2017-08-22 |
| 9697128 | Prefetch threshold for cache restoration | Harold W. Cain, III, David M. Daly, Brian R. Prasky | 2017-07-04 |
| 9652243 | Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor | Ioana Monica Burcea, Alper Buyuktosunoglu, Brian R. Prasky | 2017-05-16 |
| 9626293 | Single-thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi +4 more | 2017-04-18 |
| 9619385 | Single thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi +4 more | 2017-04-11 |
| 9529723 | Methods of cache preloading on a partition or a context switch | Harold W. Cain, III, Jason D. Zebchuk | 2016-12-27 |
| 9448835 | Thread-based cache content saving for task switching | Harold W. Cain, III, David M. Daly, Brian R. Prasky | 2016-09-20 |
| 9436501 | Thread-based cache content saving for task switching | Harold W. Cain, III, David M. Daly, Brian R. Prasky | 2016-09-06 |
| 9430240 | Pre-computation slice merging for prefetching in a computer processor | Islam Mohamed Hatem Abdulfattah Mohamed Atta, Ioana M. Baldini Soares, Kailash Gopalakrishnan | 2016-08-30 |
| 9431084 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2016-08-30 |
| 9424192 | Private memory table for reduced memory coherence traffic | David M. Daly | 2016-08-23 |
| 9418721 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2016-08-16 |
| 9411730 | Private memory table for reduced memory coherence traffic | David M. Daly | 2016-08-09 |
| 9406368 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2016-08-02 |
| 9351899 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers | 2016-05-31 |
| 9323676 | Non-data inclusive coherent (NIC) directory for cache | Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-kin Mak, Craig R. Walters | 2016-04-26 |
| 9298466 | Multi-threaded processor instruction balancing through instruction uncertainty | Alper Buyuktosunoglu, Brian R. Prasky | 2016-03-29 |