Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271717 | Loop index set merging optimization for program instructions | Bardia Mahjour, Prasanth Chatarasi, Alberto Mannari | 2025-04-08 |
| 12141513 | Method to map convolutional layers of deep neural network on a plurality of processing elements with SIMD execution units, private memories, and connected as a 2D systolic processor array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Vijayalakshmi Srinivasan, Swagath Venkataramani | 2024-11-12 |
| 11586912 | Integrated noise generation for adversarial training | Chia-Yu Chen, Pin-Yu Chen, Mingu Kang | 2023-02-21 |
| 10769238 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Vijayalakshmi Srinivasan | 2020-09-08 |
| 10489484 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Vijayalakshmi Srinivasan | 2019-11-26 |
| 10261978 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Vijayalakshmi Srinivasan | 2019-04-16 |
| 10241972 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Vijayalakshmi Srinivasan | 2019-03-26 |