Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9292445 | Non-data inclusive coherent (NIC) directory for cache | Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-kin Mak, Craig R. Walters | 2016-03-22 |
| 9182991 | Multi-threaded processor instruction balancing through instruction uncertainty | Alper Buyuktosunoglu, Brian R. Prasky | 2015-11-10 |
| 9092341 | Methods of cache preloading on a partition or a context switch | Harold W. Cain, III, Jason D. Zebchuk | 2015-07-28 |
| 9069545 | Relaxation of synchronization for iterative convergent computations | Lakshminarayanan Renganarayana | 2015-06-30 |
| 8826095 | Method and system for providing an improved store-in cache | Philip G. Emma, Wing K. Luk, Thomas R. Puzak | 2014-09-02 |
| 8627010 | Write-through cache optimized for dependence-free parallel regions | Alexandre E. Eichenberger, Alan Gara, Martin Ohmacht | 2014-01-07 |
| 8589762 | Adaptive multi-bit error correction in endurance limited memories | Jude A. Rivers | 2013-11-19 |
| 8521999 | Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history | Philip G. Emma, Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak | 2013-08-27 |
| 8516197 | Write-through cache optimized for dependence-free parallel regions | Alexandre E. Eichenberger, Alan Gara, Martin Ohmacht | 2013-08-20 |
| 8417917 | Processor core stacking for efficient collaboration | Philip G. Emma, Eren Kursun, Moinuddin K. Qureshi | 2013-04-09 |
| 8285969 | Reducing broadcasts in multiprocessors | Khubaib Khubaib, Moinuddin K. Qureshi | 2012-10-09 |
| 8108609 | Structure for implementing dynamic refresh protocols for DRAM based cache | John E. Barth, Jr., Philip G. Emma, Erik L. Hedberg, Hillery C. Hunter, Peter A. Sandon +1 more | 2012-01-31 |
| 8024513 | Method and system for implementing dynamic refresh protocols for DRAM based cache | John E. Barth, Jr., Philip G. Emma, Erik L. Hedberg, Hillery C. Hunter, Peter A. Sandon +1 more | 2011-09-20 |
| 8004884 | Iterative write pausing techniques to improve read latency of memory systems | Michele M. Franceschini, Luis A. Lastras-Montano, Moinuddin K. Qureshi | 2011-08-23 |
| 7979682 | Method and system for preventing livelock due to competing updates of prediction information | Erik R. Altman | 2011-07-12 |
| 7971033 | Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class | Erik R. Altman | 2011-06-28 |
| 7966478 | Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers | Erik R. Altman | 2011-06-21 |
| 7962695 | Method and system for integrating SRAM and DRAM architecture in set associative cache | Marc R. Faucher, Hillery C. Hunter, William Robert Reohr, Peter A. Sandon, Arnold S. Tran | 2011-06-14 |
| 7958334 | Method and apparatus for an efficient multi-path trace cache design | Galen Arthur Rasche, Jude A. Rivers | 2011-06-07 |
| 7941728 | Method and system for providing an improved store-in cache | Philip G. Emma, Wing K. Luk, Thomas R. Puzak | 2011-05-10 |
| 7930525 | Method and apparatus for an efficient multi-path trace cache design | Galen Arthur Rasche, Jude A. Rivers | 2011-04-19 |
| 7930578 | Method and system of peak power enforcement via autonomous token-based control and management | Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Zhigang Hu, Hans M. Jacobson +2 more | 2011-04-19 |
| 7657726 | Context look ahead storage structures | Philip G. Emma, Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak, Moinuddin K. Qureshi | 2010-02-02 |
| 7526610 | Sectored cache memory | Philip G. Emma, Robert K. Montoye | 2009-04-28 |
| 7516310 | Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor | Erik R. Altman | 2009-04-07 |