Issued Patents All Time
Showing 51–75 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812359 | Thru-silicon-via structures | Fen Chen, Carole D. Graas, Xiao Hu Liu | 2017-11-07 |
| 9806025 | SOI wafers with buried dielectric layers to prevent Cu diffusion | Anthony K. Stamper, John A. Fitzsimmons | 2017-10-31 |
| 9728506 | Strain engineering devices using partial depth films in through-substrate vias | Joyce C. Liu, Jennifer A. Oakley | 2017-08-08 |
| 9728450 | Insulating a via in a semiconductor substrate | Jennifer A. Oakley, Kevin S. Petrarca, Nicole R. Reardon, Andrew H. Simon | 2017-08-08 |
| 9673176 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2017-06-06 |
| 9673095 | Protected through semiconductor via (TSV) | Jennifer A. Oakley, Kevin S. Petrarca, Richard P. Volant | 2017-06-06 |
| 9671215 | Wafer to wafer alignment | John A. Fitzsimmons, Spyridon Skordas | 2017-06-06 |
| 9666563 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2017-05-30 |
| 9653432 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2017-05-16 |
| 9653431 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2017-05-16 |
| 9633925 | Visualization of alignment marks on a chip covered by a pre-applied underfill | Katsuyuki Sakuma, Jae-Woong Nah | 2017-04-25 |
| 9553054 | Strain detection structures for bonded wafers and chips | John A. Fitzsimmons, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2017-01-24 |
| 9536784 | Integrated circuit (IC) chips with through silicon vias (TSV) and method of forming the IC | Andrew J. Martin, Jennifer A. Oakley | 2017-01-03 |
| 9536829 | Programmable electrical fuse in keep out zone | Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang | 2017-01-03 |
| 9515051 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2016-12-06 |
| 9490197 | Three dimensional organic or glass interposer | William Francis Landers, Jin Ping Liu, Andrew J. Martin, Kathryn E. Schlichting, Melissa A. Smith | 2016-11-08 |
| 9461017 | Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement | John A. Fitzsimmons, Andrew H. Simon, Anthony K. Stamper | 2016-10-04 |
| 9406561 | Three dimensional integrated circuit integration using dielectric bonding first and through via formation last | Robert Hannon, Subramanian S. Iyer, Emily R. Kinser | 2016-08-02 |
| 9404953 | Structures and methods for monitoring dielectric reliability with through-silicon vias | Fen Chen, John A. Griesemer, Chandrasekharan Kothandaraman, John M. Safran, Timothy D. Sullivan | 2016-08-02 |
| 9401323 | Protected through semiconductor via (TSV) | Jennifer A. Oakley, Kevin S. Petrarca, Richard P. Volant | 2016-07-26 |
| 9401303 | Handler wafer removal by use of sacrificial inert layer | Kangguo Cheng, Jonathan E. Faltermeier, Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2016-07-26 |
| 9330946 | Method and structure of die stacking using pre-applied underfill | Michael A. Gaynes, Katsuyuki Sakuma | 2016-05-03 |
| 9263324 | 3-D integration using multi stage vias | Troy L. Graves-Abe | 2016-02-16 |
| 9263386 | Forming BEOL line fuse structure | Emily R. Kinser | 2016-02-16 |
| 9257336 | Bottom-up plating of through-substrate vias | John A. Fitzsimmons, Troy L. Graves-Abe | 2016-02-09 |