Issued Patents All Time
Showing 101–125 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8916448 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, John A. Fitzsimmons | 2014-12-23 |
| 8907494 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Christopher N. Collins, Troy L. Graves-Abe, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2014-12-09 |
| 8889542 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Troy L. Graves-Abe | 2014-11-18 |
| 8871636 | Fluorine depleted adhesion layer for metal interconnect structure | Emily R. Kinser | 2014-10-28 |
| 8859390 | Structure and method for making crack stop for 3D integrated circuits | John A. Griesemer, William Francis Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu | 2014-10-14 |
| 8853857 | 3-D integration using multi stage vias | Troy L. Graves-Abe | 2014-10-07 |
| 8841777 | Bonded structure employing metal semiconductor alloy bonding | Zhengwen Li, Zhijiong Luo, Huilong Zhu | 2014-09-23 |
| 8841200 | Simultaneously forming a through silicon via and a deep trench structure | Kangguo Cheng, Louis L. Hsu | 2014-09-23 |
| 8835194 | Leakage measurement of through silicon vias | Bhavana Bhoovaraghan, Emily R. Kinser, Sudesh Saroop | 2014-09-16 |
| 8822141 | Front side wafer ID processing | Robert Hannon, Subramanian S. Iyer, Kevin S. Petrarca, Stuart A. Sieg | 2014-09-02 |
| 8802497 | Forming semiconductor chip connections | Louis L. Hsu, Kangguo Cheng, Timothy J. Dalton, John A. Fitzsimmons | 2014-08-12 |
| 8791009 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Troy L. Graves-Abe | 2014-07-29 |
| 8791005 | Sidewalls of electroplated copper interconnects | John A. Fitzsimmons, Troy L. Graves-Abe | 2014-07-29 |
| 8771533 | Edge protection seal for bonded substrates | Emily R. Kinser, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff | 2014-07-08 |
| 8772949 | Enhanced capture pads for through semiconductor vias | John A. Griesemer, Gary LaFontant, Kevin S. Petrarca, Richard P. Volant | 2014-07-08 |
| 8765597 | Fluorine depleted adhesion layer for metal interconnect structure | Emily R. Kinser | 2014-07-01 |
| 8749059 | Semiconductor device having a copper plug | Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow | 2014-06-10 |
| 8748288 | Bonded structure with enhanced adhesion strength | Zhengwen Li, Zhijiong Luo, Huilong Zhu | 2014-06-10 |
| 8741769 | Semiconductor device having a copper plug | Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow | 2014-06-03 |
| 8738167 | 3D integrated circuit device fabrication with precisely controllable substrate removal | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu | 2014-05-27 |
| 8709936 | Method and structure of forming backside through silicon via connections | Richard P. Volant | 2014-04-29 |
| 8691691 | TSV pillar as an interconnecting structure | Troy L. Graves-Abe, William Francis Landers, Kevin S. Petrarca, Richard P. Volant | 2014-04-08 |
| 8692246 | Leakage measurement structure having through silicon vias | Bhavana Bhoovaraghan, Emily R. Kinser, Sudesh Saroop | 2014-04-08 |
| 8679611 | Edge protection seal for bonded substrates | Emily R. Kinser, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff | 2014-03-25 |
| 8679971 | Metal-contamination-free through-substrate via structure | Robert Hannon, Richard P. Volant | 2014-03-25 |