Issued Patents All Time
Showing 151–175 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8399336 | Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman +2 more | 2013-03-19 |
| 8394715 | Method of fabricating coaxial through-silicon via | Richard P. Volant, Paul F. Findeis, Kevin S. Petrarca | 2013-03-12 |
| 8386977 | Circuit design checking for three dimensional chip technology | John A. Griesemer, William Francis Landers, Kevin S. Petrarca, Richard P. Volant | 2013-02-26 |
| 8367543 | Structure and method to improve current-carrying capabilities of C4 joints | Jasvir Singh Jaspal, William Francis Landers, Thomas E. Lombardi, Hai P. Longworth, H. Bernhard Pogge +1 more | 2013-02-05 |
| 8298914 | 3D integrated circuit device fabrication using interface wafer as permanent carrier | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman +2 more | 2012-10-30 |
| 8288270 | Enhanced electromigration resistance in TSV structure and design | John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy D. Sullivan | 2012-10-16 |
| 8287980 | Edge protection seal for bonded substrates | Emily R. Kinser, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff | 2012-10-16 |
| 8242604 | Coaxial through-silicon via | Richard P. Volant, Paul F. Findeis, Kevin S. Petrarca | 2012-08-14 |
| 8236610 | Forming semiconductor chip connections | Louis L. Hsu, Kangguo Cheng, Timothy J. Dalton, John A. Fitzsimmons | 2012-08-07 |
| 8237288 | Enhanced electromigration resistance in TSV structure and design | John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy D. Sullivan | 2012-08-07 |
| 8158515 | Method of making 3D integrated circuits | Subramanian S. Iyer, Steven J. Koester, Huilong Zhu | 2012-04-17 |
| 8128868 | Grain refinement by precipitate formation in PB-free alloys of tin | — | 2012-03-06 |
| 8129256 | 3D integrated circuit device fabrication with precisely controllable substrate removal | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu | 2012-03-06 |
| 8129842 | Enhanced interconnect structure | Chih-Chao Yang, Keith Kwong Hon Wong, Haining Yang | 2012-03-06 |
| 8120175 | Soft error rate mitigation by interconnect structure | Ian D. Melville, Kevin S. Petrarca | 2012-02-21 |
| 8114707 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip | Kevin S. Petrarca, Richard P. Volant | 2012-02-14 |
| 8076756 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures | Michael Lane, Xiao Hu Liu, Thomas M. Shaw, Robert Hannon, Ian D. Melville | 2011-12-13 |
| 8039964 | Fluorine depleted adhesion layer for metal interconnect structure | Emily R. Kinser | 2011-10-18 |
| 8022543 | Underbump metallurgy for enhanced electromigration resistance | Robert Hannon, Emily R. Kinser, Ian D. Melville | 2011-09-20 |
| 8017997 | Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via | Ramachandra Divakaruni, Jeffrey P. Gambino, Kevin S. Petrarca | 2011-09-13 |
| 7955955 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures | Michael Lane, Xiao Hu Liu, Thomas M. Shaw, Robert Hannon, Ian D. Melville | 2011-06-07 |
| 7939369 | 3D integration structure and method using bonded metal planes | Subramanian S. Iyer | 2011-05-10 |
| 7923836 | BLM structure for application to copper pad | Tien-Jen Cheng, Roger A. Quon | 2011-04-12 |
| 7919356 | Method and structure to reduce cracking in flip chip underfill | Robert Hannon, Dae Young Jung, Ian D. Melville | 2011-04-05 |
| 7900809 | Solder interconnection array with optimal mechanical integrity | Glenn G. Daves, David L. Edwards, Frank L. Pompeo | 2011-03-08 |