Issued Patents All Time
Showing 126–150 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8674515 | 3D integrated circuits structure | Subramanian S. Iyer, Steven J. Koester, Huilong Zhu | 2014-03-18 |
| 8664081 | Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman +2 more | 2014-03-04 |
| 8633580 | Integrated void fill for through silicon via | Richard P. Volant, Kevin S. Petrarca | 2014-01-21 |
| 8629553 | 3D integrated circuit device fabrication with precisely controllable substrate removal | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu | 2014-01-14 |
| 8613996 | Polymeric edge seal for bonded substrates | Thomas Houghton, Nitin Parbhoo, Richard P. Volant | 2013-12-24 |
| 8610283 | Semiconductor device having a copper plug | Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow | 2013-12-17 |
| 8609537 | Integrated void fill for through silicon via | Richard P. Volant, Kevin S. Petrarca | 2013-12-17 |
| 8586431 | Three dimensional integration and methods of through silicon via creation | Emily R. Kinser, Richard S. Wise, Hakeem Yusuff | 2013-11-19 |
| 8569154 | Three dimensional integration and methods of through silicon via creation | Emily R. Kinser, Richard S. Wise, Hakeem Yusuff | 2013-10-29 |
| 8563423 | Fluorine depleted adhesion layer for metal interconnect structure | Emily R. Kinser | 2013-10-22 |
| 8563403 | Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last | Spyridon Skordas, Richard P. Volant, Kevin R. Winstel | 2013-10-22 |
| 8546961 | Alignment marks to enable 3D integration | Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William Francis Landers, Kevin S. Petrarca +2 more | 2013-10-01 |
| 8507325 | Co-axial restraint for connectors within flip-chip packages | John A. Fitzsimmons | 2013-08-13 |
| 8492869 | 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman +2 more | 2013-07-23 |
| 8492878 | Metal-contamination-free through-substrate via structure | Robert Hannon, Richard P. Volant | 2013-07-23 |
| 8492252 | Three dimensional integration and methods of through silicon via creation | Emily R. Kinser, Richard S. Wise, Hakeem Yusuff | 2013-07-23 |
| 8492241 | Method for simultaneously forming a through silicon via and a deep trench structure | Kangguo Cheng, Louis L. Hsu | 2013-07-23 |
| 8487425 | Optimized annular copper TSV | Paul S. Andry, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Cornelia K. Tsang +1 more | 2013-07-16 |
| 8476168 | Non-conformal hardmask deposition for through silicon etch | Troy L. Graves-Abe | 2013-07-02 |
| 8461695 | Grain refinement by precipitate formation in Pb-free alloys of tin | — | 2013-06-11 |
| 8455270 | 3D multiple die stacking | Robert Hannon, Subramanian S. Iyer | 2013-06-04 |
| 8455356 | Integrated void fill for through silicon via | Richard P. Volant, Kevin S. Petrarca | 2013-06-04 |
| 8445374 | Soft error rate mitigation by interconnect structure | Ian D. Melville, Kevin S. Petrarca | 2013-05-21 |
| 8415238 | Three dimensional integration and methods of through silicon via creation | Emily R. Kinser, Richard S. Wise, Hakeem Yusuff | 2013-04-09 |
| 8399180 | Three dimensional integration with through silicon vias having multiple diameters | Ramona Kei, Emily R. Kinser, Anthony D. Lisi, Richard S. Wise, Hakeem Yusuff | 2013-03-19 |