Issued Patents All Time
Showing 76–100 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9257361 | In-situ thermoelectric cooling | Emily R. Kinser, JoAnn M. Rolick-DiGiacomio, Charu Tejwani | 2016-02-09 |
| 9252133 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Christopher N. Collins, Troy L. Graves-Abe, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2016-02-02 |
| 9219023 | 3D chip stack having encapsulated chip-in-chip | Kangguo Cheng, Louis L. Hsu | 2015-12-22 |
| 9214388 | Bonded structure employing metal semiconductor alloy bonding | Zhengwen Li, Zhijiong Luo, Huilong Zhu | 2015-12-15 |
| 9214435 | Via structure for three-dimensional circuit integration | Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel | 2015-12-15 |
| 9159674 | Bonded structure with enhanced adhesion strength | Zhengwen Li, Zhijiong Luo, Huilong Zhu | 2015-10-13 |
| 9105517 | Wafer to wafer alignment by LED/LSD devices | John A. Fitzsimmons, Spyridon Skordas | 2015-08-11 |
| 9093503 | Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure | Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Kevin S. Petrarca, Anthony K. Stamper | 2015-07-28 |
| 9060457 | Sidewalls of electroplated copper interconnects | John A. Fitzsimmons, Troy L. Graves-Abe | 2015-06-16 |
| 9059333 | Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding | Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2015-06-16 |
| 9059175 | Forming BEOL line fuse structure | Emily R. Kinser | 2015-06-16 |
| 9059167 | Structure and method for making crack stop for 3D integrated circuits | John A. Griesemer, William Francis Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu | 2015-06-16 |
| 9055703 | Sidewalls of electroplated copper interconnects | John A. Fitzsimmons, Troy L. Graves-Abe | 2015-06-09 |
| 9047938 | Phase change memory management | Eren Kursun, Gary W. Maier, Bipin Rajendran | 2015-06-02 |
| 9040418 | Enhanced capture pads for through semiconductor vias | John A. Griesemer, Gary LaFontant, Kevin S. Petrarca, Richard P. Volant | 2015-05-26 |
| 9040407 | Sidewalls of electroplated copper interconnects | John A. Fitzsimmons, Troy L. Graves-Abe | 2015-05-26 |
| 9035465 | Forming semiconductor chip connections | Kangguo Cheng, Timothy J. Dalton, John A. Fitzsimmons, Louis L. Hsu | 2015-05-19 |
| 8999764 | Ionizing radiation blocking in IC chip to reduce soft errors | Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell | 2015-04-07 |
| 8970041 | Co-axial restraint for connectors within flip-chip packages | John A. Fitzsimmons | 2015-03-03 |
| 8970011 | Method and structure of forming backside through silicon via connections | Richard P. Volant | 2015-03-03 |
| 8962448 | Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier | Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman +2 more | 2015-02-24 |
| 8956973 | Bottom-up plating of through-substrate vias | John A. Fitzsimmons, Troy L. Graves-Abe | 2015-02-17 |
| 8951906 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Troy L. Graves-Abe | 2015-02-10 |
| 8933562 | In-situ thermoelectric cooling | Emily R. Kinser, JoAnn M. Rolick-DiGiacomio, Charu Tejwani | 2015-01-13 |
| 8922019 | Semiconductor device having a copper plug | Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow | 2014-12-30 |