Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9984324 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-05-29 |
| 9965718 | Providing transposable access to a synapse array using a recursive array layout | John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha | 2018-05-08 |
| 9940302 | Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2018-04-10 |
| 9924490 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-03-20 |
| 9886662 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2018-02-06 |
| 9881252 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2018-01-30 |
| 9852006 | Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-12-26 |
| 9818058 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2017-11-14 |
| 9797946 | Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2017-10-24 |
| 9792251 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-10-17 |
| 9747545 | Self-timed, event-driven neurosynaptic core controller | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-08-29 |
| 9588937 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-03-07 |
| 9563841 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2017-02-07 |
| 9558443 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2017-01-31 |
| 9466022 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2016-10-11 |
| 9424284 | Mapping neural dynamics of a neural model on to a coarsely grained look-up table | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2016-08-23 |
| 9373073 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-06-21 |
| 9368489 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2016-06-14 |
| 9363137 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more | 2016-06-07 |
| 9269044 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, Rajit Manohar, Paul A. Merolla, Dharmendra S. Modha, Alyosha Molnar +1 more | 2016-02-23 |
| 9244124 | Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2016-01-26 |
| 9239984 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-01-19 |
| 9218564 | Providing transposable access to a synapse array using a recursive array layout | John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha | 2015-12-22 |
| 9189729 | Scalable neural hardware for the noisy-OR model of Bayesian networks | Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha | 2015-11-17 |
| 9160617 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more | 2015-10-13 |