Issued Patents All Time
Showing 26–50 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Steven K. Esser, Bryan L. Jackson +3 more | 2021-04-27 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-02-23 |
| 10839287 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2020-11-17 |
| 10838860 | Memory-mapped interface to message-passing computing systems | Filipp A. Akopyan, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla, Dharmendra S. Modha +1 more | 2020-11-17 |
| 10831595 | Performing error detection during deterministic program execution | Andrew S. Cassidy, Dharmendra S. Modha, Jun Sawada | 2020-11-10 |
| 10785745 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2020-09-22 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-08-25 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2020-08-11 |
| 10713561 | Multiplexing physical neurons to optimize power and area | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2020-07-14 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2020-05-12 |
| 10621489 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2020-04-14 |
| 10504021 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, Rajit Manohar, Paul A. Merolla, Dharmendra S. Modha, Alyosha Molnar +1 more | 2019-12-10 |
| 10454759 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2019-10-22 |
| 10452540 | Memory-mapped interface for message passing computing systems | Filipp A. Akopyan, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla, Dharmendra S. Modha +1 more | 2019-10-22 |
| 10410109 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2019-09-10 |
| 10331998 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2019-06-25 |
| 10282658 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2019-05-07 |
| 10204118 | Mapping neural dynamics of a neural model on to a coarsely grained look-up table | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2019-02-12 |
| 10198692 | Scalable neural hardware for the noisy-OR model of Bayesian networks | Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha | 2019-02-05 |
| 10176063 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more | 2019-01-08 |
| 10169700 | Neuromorphic network comprising asynchronous routers and synchronous core circuits | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2019-01-01 |
| 10102474 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-10-16 |
| 9992057 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-06-05 |