Issued Patents All Time
Showing 51–75 of 254 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2021-02-23 |
| 10891544 | Event-driven universal neural network circuit | — | 2021-01-12 |
| 10885424 | Structural plasticity in spiking neural networks with symmetric dual of an electronic neuron | — | 2021-01-05 |
| 10846567 | Scene understanding using a neurosynaptic system | Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser | 2020-11-24 |
| 10838860 | Memory-mapped interface to message-passing computing systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla +1 more | 2020-11-17 |
| 10839287 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla | 2020-11-17 |
| 10832151 | Implementing stochastic networks using magnetic tunnel junctions | Bryan L. Jackson | 2020-11-10 |
| 10832125 | Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm | Arnon Amir, Rathinakumar Appuswamy, Pallab Datta, Myron D. Flickner, Paul A. Merolla +1 more | 2020-11-10 |
| 10832121 | Transform for a neurosynaptic core circuit | Rathinakumar Appuswamy, Myron D. Flickner | 2020-11-10 |
| 10831595 | Performing error detection during deterministic program execution | Andrew S. Cassidy, John V. Arthur, Jun Sawada | 2020-11-10 |
| 10810487 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2020-10-20 |
| 10785745 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2020-09-22 |
| 10782726 | Optimizing core utilization in neurosynaptic systems | Arnon Amir, Pallab Datta, Nimrod Megiddo | 2020-09-22 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-09-08 |
| 10755166 | Transform architecture for multiple neurosynaptic core circuits | Rathinakumar Appuswamy, Myron D. Flickner | 2020-08-25 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-08-25 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2020-08-11 |
| 10725494 | Optimizing neurosynaptic networks | Arnon Amir, Pallab Datta | 2020-07-28 |
| 10713561 | Multiplexing physical neurons to optimize power and area | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla | 2020-07-14 |
| 10679120 | Power driven synaptic network synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Gi-Joon Nam | 2020-06-09 |
| 10678741 | Coupling parallel event-driven computation with serial computation | Bryan L. Jackson, Norman J. Pass | 2020-06-09 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2020-05-12 |
| 10635969 | Core utilization optimization by dividing computational blocks across cores | Arnon Amir, Pallab Datta, Nimrod Megiddo | 2020-04-28 |
| 10628732 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2020-04-21 |