Issued Patents All Time
Showing 51–75 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8775996 | Direct current circuit analysis based clock network design | Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle +2 more | 2014-07-08 |
| 8769457 | Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design | Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan | 2014-07-01 |
| 8769468 | Automatic generation of wire tag lists for a metal stack | Robert M. Averill, III, Eric Jason Fluhr, Zhuo Li, Tuhin Mahmud, Jose L. P. Neves +3 more | 2014-07-01 |
| 8683411 | Electronic design automation object placement with partially region-constrained objects | John L. McCann, Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Natarajan Viswanathan | 2014-03-25 |
| 8677299 | Latch clustering with proximity to local clock buffers | Zhuo Li, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-18 |
| 8677305 | Designing a robust power efficient clock distribution network | Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle +2 more | 2014-03-18 |
| 8667441 | Clock optimization with local clock buffer control optimization | Zhuo Li, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-04 |
| 8656334 | Multiple threshold voltage cell families based integrated circuit design | Zhuo Li, Arjen A. Mets, Ying Zhou | 2014-02-18 |
| 8640075 | Early design cycle optimzation | Robert M. Averill, III, Zhuo Li, Jose L. Neves, Stephen T. Quay | 2014-01-28 |
| 8601425 | Solving congestion using net grouping | Zhuo Li, Chin Ngai Sze, Yaoguang Wei | 2013-12-03 |
| 8595675 | Local objective optimization in global placement of an integrated circuit design | Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan | 2013-11-26 |
| 8589848 | Datapath placement using tiered assignment | Zhuo Li, Natarajan Viswanathan, Samuel I. Ward | 2013-11-19 |
| 8584070 | Evaluating routing congestion based on average global edge congestion histograms | Zhuo Li, Lakshmi N. Reddy, Chin Ngai Sze, Yaoguang Wei | 2013-11-12 |
| 8539400 | Routability using multiplexer structures | Victor N. Kravets, Zhuo Li, Louise H. Trevillyan, Ying Zhou | 2013-09-17 |
| 8495534 | Post-placement cell shifting | Zhuo Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A. Roy +3 more | 2013-07-23 |
| 8495548 | Multi-patterning lithography aware cell placement in integrated circuit design | Kanak B. Agarwal, Zhuo Li, Gi-Joon Nam, Natarajan Viswanathan | 2013-07-23 |
| 8458634 | Latch clustering with proximity to local clock buffers | Zhuo Li, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2013-06-04 |
| 8443324 | Routing and timing using layer ranges | Shiyan Hu, Zhuo Li, Chin Ngai Sze | 2013-05-14 |
| 8418108 | Accuracy pin-slew mode for gate delay calculation | Zhuo Li, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan +1 more | 2013-04-09 |
| 8418113 | Consideration of local routing and pin access during VLSI global routing | Zhuo Li, Chin Ngai Sze, Yaoguang Wei | 2013-04-09 |
| 8386985 | Timing driven routing in integrated circuit design | Zhuo Li, Stephen T. Quay, Ying Zhou | 2013-02-26 |
| 8365120 | Resolving global coupling timing and slew violations for buffer-dominated designs | Joachim Clabes, Zhuo Li, Tuhin Mahmud, Stephen T. Quay | 2013-01-29 |
| 8347249 | Incremental timing optimization and placement | Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Natarajan Viswanathan | 2013-01-01 |
| 8347257 | Detailed routability by cell placement | Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy +4 more | 2013-01-01 |
| 8112732 | System and computer program product for diffusion based cell placement migration | Haoxing Ren, Paul Gerard Villarubia | 2012-02-07 |