Issued Patents All Time
Showing 76–100 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8108819 | Object placement in integrated circuit design | Gi-Joon Nam, Jarrod A. Roy, Natarajan Vishvanathan | 2012-01-31 |
| 8108818 | Method and system for point-to-point fast delay estimation for VLSI circuits | Chin Ngai Sze, Michael D. Moffitt, Zhuo Li | 2012-01-31 |
| 8091059 | Method for diffusion based cell placement migration | Haxoing Ren, Paul Gerard Villarubia | 2012-01-03 |
| 8037438 | Techniques for parallel buffer insertion | Zhuo Li, Damir A. Jamsek, Chin Ngai Sze, Ying Zhou | 2011-10-11 |
| 8015532 | Optimal timing-driven cloning under linear delay model | Zhuo Li, David A. Papa, Chin Ngai Sze | 2011-09-06 |
| 8010926 | Clock power minimization with regular physical placement of clock repeater components | Ruchir Puri, Shyam Ramji, Ashish Singh, Chin Ngai Sze | 2011-08-30 |
| 7934188 | Legalization of VLSI circuit placement with blockages using hierarchical row slicing | Michael W. Dotson, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan | 2011-04-26 |
| 7895557 | Concurrent buffering and layer assignment in integrated circuit layout | Zhuo Li, Tuhin Mahmud, Stephen T. Quay, Paul G. Villarrubla | 2011-02-22 |
| 7890905 | Slew constrained minimum cost buffering | Arvind K. Karandikar, Tuhin Mahmud, Stephen T. Quay, Chin Ngai Sze | 2011-02-15 |
| 7882475 | Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors | Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia, Natarajan Viswanathan | 2011-02-01 |
| 7761832 | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model | Zhuo Li, Tao Luo, David A. Papa, Chin Ngai Sze | 2010-07-20 |
| 7707530 | Incremental timing-driven, physical-synthesis using discrete optimization | Zhuo Li, Michael D. Moffitt, David A. Papa | 2010-04-27 |
| 7676780 | Techniques for super fast buffer insertion | Zhuo Li, Stephen T. Quay | 2010-03-09 |
| 7624366 | Clock aware placement | David J. Hathaway, William R. Migatz, Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia | 2009-11-24 |
| 7549137 | Latch placement for high performance and low power circuits | Shyam Ramji, Chin Ngai Sze, Paul G. Villarrubia | 2009-06-16 |
| 7484199 | Buffer insertion to reduce wirelength in VLSI circuits | Tuhin Mahmud, Stephen T. Quay | 2009-01-27 |
| 7467369 | Constrained detailed placement | Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia | 2008-12-16 |
| 7464356 | Method and apparatus for diffusion based cell placement migration | Haoxing Ren, Paul G. Villarrubia | 2008-12-09 |
| 7448007 | Slew constrained minimum cost buffering | Arvind K. Karandikar, Tuhin Mahmud, Stephen T. Quay, Chin Ngai Sze | 2008-11-04 |
| 7392493 | Techniques for super fast buffer insertion | Zhuo Li, Stephen T. Quay | 2008-06-24 |
| 7299442 | Probabilistic congestion prediction with partial blockages | Zhuo Li, Stephen T. Quay | 2007-11-20 |
| 7296252 | Clustering techniques for faster and better placement of VLSI circuits | Gi-Joon Nam, Sherief Reda, Paul G. Villarrubia | 2007-11-13 |
| 7137081 | Method and apparatus for performing density-biased buffer insertion in an integrated circuit design | Milos Hrkic, Stephen T. Quay | 2006-11-14 |
| 7127696 | Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management | Rama Gopal Gandham, Milos Hrkic, Stephen T. Quay | 2006-10-24 |
| 7073144 | Stability metrics for placement to quantify the stability of placement algorithms | Gi-Joon Nam, Paul G. Villarrubia, Mehmet Can Yildiz | 2006-07-04 |