| 11775720 |
Integrated circuit development using machine learning-based prediction of power, performance, and area |
Saiful Islam, Abraham Mathews, Geoffrey Wang |
2023-10-03 |
| 11205092 |
Clustering simulation failures for triage and debugging |
Bryan G. Hickerson, John Richard Reysa, Mohamed Baker Alawieh, Brian L. Kozitza, Erica Stuecheli +1 more |
2021-12-21 |
| 9092591 |
Automatic generation of wire tag lists for a metal stack |
Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Zhuo Li, Jose L. P. Neves +3 more |
2015-07-28 |
| 8881089 |
Physical synthesis optimization with fast metric check |
Charles J. Alpert, Glenn R. Bee, Zhuo Li, Stephen T. Quay, Lakshmi N. Reddy +2 more |
2014-11-04 |
| 8769468 |
Automatic generation of wire tag lists for a metal stack |
Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Zhuo Li, Jose L. P. Neves +3 more |
2014-07-01 |
| 8365120 |
Resolving global coupling timing and slew violations for buffer-dominated designs |
Charles J. Alpert, Joachim Clabes, Zhuo Li, Stephen T. Quay |
2013-01-29 |
| 7895557 |
Concurrent buffering and layer assignment in integrated circuit layout |
Charles J. Alpert, Zhuo Li, Stephen T. Quay, Paul G. Villarrubla |
2011-02-22 |
| 7890905 |
Slew constrained minimum cost buffering |
Charles J. Alpert, Arvind K. Karandikar, Stephen T. Quay, Chin Ngai Sze |
2011-02-15 |
| 7484199 |
Buffer insertion to reduce wirelength in VLSI circuits |
Charles J. Alpert, Stephen T. Quay |
2009-01-27 |
| 7448007 |
Slew constrained minimum cost buffering |
Charles J. Alpert, Arvind K. Karandikar, Stephen T. Quay, Chin Ngai Sze |
2008-11-04 |
