Issued Patents All Time
Showing 101–119 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7065730 | Porosity aware buffered steiner tree construction | Rama Gopal Gandham, Jiang Hu, Stephen T. Quay | 2006-06-20 |
| 7036104 | Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes | Steven Thomas Quay, Anirudh Devgan | 2006-04-25 |
| 7020861 | Latch placement technique for reduced clock signal skew | Gary R. Ellis, Gi-Joon Nam, Paul G. Villarrubia | 2006-03-28 |
| 6996512 | Practical methodology for early buffer and wire resource allocation | Jiang Hu, Paul G. Villarrubia | 2006-02-07 |
| 6968306 | Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model | Anirudh Devgan, Chandramouli V. Kashyap | 2005-11-22 |
| 6950996 | Interconnect delay and slew metrics based on the lognormal distribution | Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu | 2005-09-27 |
| 6915496 | Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique | Chong-Nuen Chu, Rama Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap +1 more | 2005-07-05 |
| 6915361 | Optimal buffered routing path constructions for single and multiple clock domains systems | Soha Hassoun | 2005-07-05 |
| 6898774 | Buffer insertion with adaptive blockage avoidance | Rama Gopal Gandham, Jiang Hu, Stephen T. Quay | 2005-05-24 |
| 6868533 | Method and system for extending delay and slew metrics to ramp inputs | Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu | 2005-03-15 |
| 6807659 | Robust delay metric for RC circuits | Chandramouli V. Kashyap, Ying Liu | 2004-10-19 |
| 6671867 | Analytical constraint generation for cut-based global placement | Gi-Joon Nam, Paul G. Villarrubia | 2003-12-30 |
| 6591411 | Apparatus and method for determining buffered steiner trees for complex circuits | Rama Gopal Gandham, Jiang Hu, Stephen T. Quay, Andrew J. Sullivan | 2003-07-08 |
| 6560752 | Apparatus and method for buffer library selection for use in buffer insertion | Rama Gopal Gandham, Jose L. Neves, Stephen T. Quay | 2003-05-06 |
| 6434729 | Two moment RC delay metric for performance optimization | Anirudh Devgan, Chandramouli V. Kashyap | 2002-08-13 |
| 6401234 | Method and system for re-routing interconnects within an integrated circuit design having blockages and bays | Rama Gopal Gandham, Jiang Hu, Jose L. Neves, Stephen T. Quay | 2002-06-04 |
| 6347393 | Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation | Anirudh Devgan, Stephen T. Quay | 2002-02-12 |
| 6117182 | Optimum buffer placement for noise avoidance | Stephen T. Quay, Anirudh Devgan | 2000-09-12 |
| 6044209 | Method and system for segmenting wires prior to buffer insertion | Stephen T. Quay, Anirudh Devgan | 2000-03-28 |