Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12339701 | Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis | Yi-Xiao Ding, Natarajan Viswanathan, Charles J. Alpert | 2025-06-24 |
| 12321193 | Hierarchically-aware buffering for clock structures | Yi-Xiao Ding, Natarajan Viswanathan, Charles J. Alpert | 2025-06-03 |
| 11520959 | Pruning of buffering candidates for improved efficiency of evaluation | Yi-Xiao Ding, Zhuo Li, Jhih-Rong Gao | 2022-12-06 |
| 11514222 | Cell-width aware buffer insertion technique for narrow channels | Yi-Xiao Ding, Jhih-Rong Gao, Zhuo Li | 2022-11-29 |