Issued Patents All Time
Showing 51–75 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10552740 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Dharmendra S. Modha, Gi-Joon Nam | 2020-02-04 |
| 10509878 | Systems and methods for routing track assignment | Yi-Xiao Ding, Wen-Hao Liu | 2019-12-17 |
| 10460063 | Integrated circuit routing based on enhanced topology | Wen-Hao Liu, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz | 2019-10-29 |
| 10460064 | Partition-aware grid graph based hierarchical global routing | Gracieli Posser, Wen-Hao Liu, Mehmet Can Yildiz | 2019-10-29 |
| 10460065 | Routing topology generation using spine-like tree structure | Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Charles J. Alpert | 2019-10-29 |
| 10460066 | Routing framework to resolve single-entry constraint violations for integrated circuit designs | Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Mehmet Can Yildiz | 2019-10-29 |
| 10402533 | Placement of cells in a multi-level routing tree | William Robert Reece, Yi-Xiao Ding, Thomas Andrew Newton, Charles J. Alpert | 2019-09-03 |
| 10380287 | Systems and methods for modifying a balanced clock structure | Dirk Meyer, Charles J. Alpert | 2019-08-13 |
| 10354183 | Power-driven synthesis under latency constraints | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Dharmendra S. Modha, Gi-Joon Nam | 2019-07-16 |
| 10354040 | Systems and methods for clock tree generation with buffers and inverters | Amin Farshidi, Thomas Andrew Newton, Charles J. Alpert | 2019-07-16 |
| 10318693 | Balanced scaled-load clustering | Natarajan Viswanathan, Charles J. Alpert, William Robert Reece, Thomas Andrew Newton | 2019-06-11 |
| 10289795 | Routing tree topology generation | Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Charles J. Alpert | 2019-05-14 |
| 10289775 | Systems and methods for assigning clock taps based on timing | Brian Wilson, Charles J. Alpert | 2019-05-14 |
| 10282506 | Systems and methods for clock tree clustering | Dirk Meyer, Charles J. Alpert | 2019-05-07 |
| 10216880 | Systems and methods for power efficient flop clustering | Wen-Hao Liu, Charles J. Alpert, Brian Wilson | 2019-02-26 |
| 10198551 | Clock cell library selection | Amin Farshidi, Charles J. Alpert, William Robert Reece | 2019-02-05 |
| 10102328 | System and method for constructing spanning trees | Wen-Hao Liu, Charles J. Alpert, Mehmet Can Yildiz | 2018-10-16 |
| 10095824 | Systems and methods for symmetric H-tree construction with complicated routing blockages | Wen-Hao Liu, Charles J. Alpert, Brian Wilson | 2018-10-09 |
| 10031994 | Systems and methods for congestion and routability aware detailed placement | Wen-Hao Liu, Jhih-Rong Gao, Mehmet Can Yildiz, Charles J. Alpert | 2018-07-24 |
| 9946824 | Efficient Ceff model for gate output slew computation in early synthesis | Charles J. Alpert, Sani R. Nassif, Yilin Zhang, Ying Zhou | 2018-04-17 |
| 9875326 | Addressing coupled noise-based violations with buffering in a batch environment | Charles J. Alpert, William E. Dougherty, Jr., Stephen T. Quay, Ying Zhou | 2018-01-23 |
| 9785738 | System and method for evaluating spanning trees | Charles J. Alpert, Wing-Kai Chow, Wen-Hao Liu, Derong Liu | 2017-10-10 |
| 9438269 | Accelerating codeset conversion in a computing environment | Jian Li, Su Liu, Shunguo Yan | 2016-09-06 |
| 9106560 | Solving network traffic congestion using device grouping | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2015-08-11 |
| 9098669 | Boundary latch and logic placement to satisfy timing constraints | Charles J. Alpert, Mark D. Aubel, Gregory F. Ford, Chin Ngai Sze, Paul G. Villarrubia +1 more | 2015-08-04 |