Issued Patents All Time
Showing 76–100 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9092591 | Automatic generation of wire tag lists for a metal stack | Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Tuhin Mahmud, Jose L. P. Neves +3 more | 2015-07-28 |
| 9047436 | Computer-based modeling of integrated circuit congestion and wire distribution for products and services | Charles J. Alpert, Chin Ngai Sze, Jia Lin Wang, Yaoguang Wei | 2015-06-02 |
| 9038009 | Early design cycle optimization | Charles J. Alpert, Robert M. Averill, III, Jose L. Neves, Stephen T. Quay | 2015-05-19 |
| 9026976 | Congestion aware routing using random points | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2015-05-05 |
| 8954912 | Structured placement of latches/flip-flops to minimize clock power in high-performance designs | Charles J. Alpert, Gi-Joon Nam, Shyam Ramji, Chin Ngai Sze, Paul G. Villarrubia +1 more | 2015-02-10 |
| 8949762 | Computer-based modeling of integrated circuit congestion and wire distribution for products and services | Charles J. Alpert, Chin Ngai Sze, Jia Lin Wang, Yaoguang Wei | 2015-02-03 |
| 8938702 | Timing driven routing for noise reduction in integrated circuit design | Andre Hogan, Andrew D. Huber, Karsten Muuss, Sven Peyer, Christian Schulte +1 more | 2015-01-20 |
| 8930873 | Creating regional routing blockages in integrated circuit design | Charles J. Alpert, Gi-Joon Nam, Sven Peyer, Sourav Saha, Chin Ngai Sze +1 more | 2015-01-06 |
| 8897998 | Solving traffic congestion using vehicle grouping | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2014-11-25 |
| 8892344 | Solving traffic congestion using vehicle grouping | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2014-11-18 |
| 8881089 | Physical synthesis optimization with fast metric check | Charles J. Alpert, Glenn R. Bee, Tuhin Mahmud, Stephen T. Quay, Lakshmi N. Reddy +2 more | 2014-11-04 |
| 8831875 | Solving traffic congestion using vehicle grouping | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2014-09-09 |
| 8826215 | Routing centric design closure | Charles J. Alpert, Gi-Joon Nam, Chin Ngai Sze, Paul G. Villarrubia | 2014-09-02 |
| 8793636 | Placement of structured nets | Charles J. Alpert, Myung-Chul Kim, Natarajan Viswanathan, Samuel I. Ward | 2014-07-29 |
| 8782584 | Post-placement cell shifting | Charles J. Alpert, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A. Roy +3 more | 2014-07-15 |
| 8775996 | Direct current circuit analysis based clock network design | Charles J. Alpert, Joseph N. Kozhaya, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle +2 more | 2014-07-08 |
| 8769468 | Automatic generation of wire tag lists for a metal stack | Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Tuhin Mahmud, Jose L. P. Neves +3 more | 2014-07-01 |
| 8677305 | Designing a robust power efficient clock distribution network | Charles J. Alpert, Joseph N. Kozhaya, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle +2 more | 2014-03-18 |
| 8677299 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-18 |
| 8667441 | Clock optimization with local clock buffer control optimization | Charles J. Alpert, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-04 |
| 8656334 | Multiple threshold voltage cell families based integrated circuit design | Charles J. Alpert, Arjen A. Mets, Ying Zhou | 2014-02-18 |
| 8640075 | Early design cycle optimzation | Charles J. Alpert, Robert M. Averill, III, Jose L. Neves, Stephen T. Quay | 2014-01-28 |
| 8635577 | Timing refinement re-routing | Michael A. Kazda, Gi-Joon Nam, Ying Zhou | 2014-01-21 |
| 8601425 | Solving congestion using net grouping | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2013-12-03 |
| 8589848 | Datapath placement using tiered assignment | Charles J. Alpert, Natarajan Viswanathan, Samuel I. Ward | 2013-11-19 |