Issued Patents All Time
Showing 101–123 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8584070 | Evaluating routing congestion based on average global edge congestion histograms | Charles J. Alpert, Lakshmi N. Reddy, Chin Ngai Sze, Yaoguang Wei | 2013-11-12 |
| 8539400 | Routability using multiplexer structures | Charles J. Alpert, Victor N. Kravets, Louise H. Trevillyan, Ying Zhou | 2013-09-17 |
| 8495534 | Post-placement cell shifting | Charles J. Alpert, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A. Roy +3 more | 2013-07-23 |
| 8495548 | Multi-patterning lithography aware cell placement in integrated circuit design | Kanak B. Agarwal, Charles J. Alpert, Gi-Joon Nam, Natarajan Viswanathan | 2013-07-23 |
| 8458634 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2013-06-04 |
| 8443324 | Routing and timing using layer ranges | Charles J. Alpert, Shiyan Hu, Chin Ngai Sze | 2013-05-14 |
| 8418108 | Accuracy pin-slew mode for gate delay calculation | Charles J. Alpert, Gi-Joon Nam, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan +1 more | 2013-04-09 |
| 8418113 | Consideration of local routing and pin access during VLSI global routing | Charles J. Alpert, Chin Ngai Sze, Yaoguang Wei | 2013-04-09 |
| 8386985 | Timing driven routing in integrated circuit design | Charles J. Alpert, Stephen T. Quay, Ying Zhou | 2013-02-26 |
| 8370782 | Buffer-aware routing in integrated circuit design | Chuck ALPERT, Michael D. Moffitt, Chin Ngai Sze, Paul G. Villarrubia | 2013-02-05 |
| 8365118 | Broken-spheres methodology for improved failure probability analysis in multi-fail regions | Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif | 2013-01-29 |
| 8365120 | Resolving global coupling timing and slew violations for buffer-dominated designs | Charles J. Alpert, Joachim Clabes, Tuhin Mahmud, Stephen T. Quay | 2013-01-29 |
| 8347249 | Incremental timing optimization and placement | Charles J. Alpert, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Natarajan Viswanathan | 2013-01-01 |
| 8347257 | Detailed routability by cell placement | Charles J. Alpert, Andrew D. Huber, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy +4 more | 2013-01-01 |
| 8108818 | Method and system for point-to-point fast delay estimation for VLSI circuits | Chin Ngai Sze, Charles J. Alpert, Michael D. Moffitt | 2012-01-31 |
| 8037438 | Techniques for parallel buffer insertion | Charles J. Alpert, Damir A. Jamsek, Chin Ngai Sze, Ying Zhou | 2011-10-11 |
| 8015532 | Optimal timing-driven cloning under linear delay model | Charles J. Alpert, David A. Papa, Chin Ngai Sze | 2011-09-06 |
| 7895557 | Concurrent buffering and layer assignment in integrated circuit layout | Charles J. Alpert, Tuhin Mahmud, Stephen T. Quay, Paul G. Villarrubla | 2011-02-22 |
| 7761832 | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model | Charles J. Alpert, Tao Luo, David A. Papa, Chin Ngai Sze | 2010-07-20 |
| 7707530 | Incremental timing-driven, physical-synthesis using discrete optimization | Charles J. Alpert, Michael D. Moffitt, David A. Papa | 2010-04-27 |
| 7676780 | Techniques for super fast buffer insertion | Charles J. Alpert, Stephen T. Quay | 2010-03-09 |
| 7392493 | Techniques for super fast buffer insertion | Charles J. Alpert, Stephen T. Quay | 2008-06-24 |
| 7299442 | Probabilistic congestion prediction with partial blockages | Charles J. Alpert, Stephen T. Quay | 2007-11-20 |