Issued Patents All Time
Showing 26–50 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10990721 | Delay dependence in physically aware cell cloning | William Robert Reece, Thomas Andrew Newton | 2021-04-27 |
| 10963620 | Buffer insertion technique to consider edge spacing and stack via design rules | Yi-Xiao Ding, Jhih-Rong Gao | 2021-03-30 |
| 10963617 | Modifying route topology to fix clock tree violations | Andrew Mark Chapman, William Robert Reece, Natarajan Viswanathan, Mehmet Can Yildiz, Gracieli Posser | 2021-03-30 |
| 10963618 | Multi-dimension clock gate design in clock tree synthesis | Amin Farshidi, William Robert Reece, Kwangsoo Han, Thomas Andrew Newton | 2021-03-30 |
| 10936777 | Unified improvement scoring calculation for rebuffering an integrated circuit design | Jhih-Rong Gao, Yi-Xiao Ding | 2021-03-02 |
| 10936783 | Runtime efficient circuit placement search location selection | Andrew Mark Chapman | 2021-03-02 |
| 10929589 | Generating routing structure for clock network based on edge intersection detection | Dirk Meyer | 2021-02-23 |
| 10885250 | Clock gate placement with data path awareness | David White, Andrew Mark Chapman, Thomas Andrew Newton | 2021-01-05 |
| 10885257 | Routing congestion based on via spacing and pin density | Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz | 2021-01-05 |
| 10860764 | Layer assignment technique to improve timing in integrated circuit design | Yi-Xiao Ding, Jhih-Rong Gao | 2020-12-08 |
| 10860757 | Multicorner skew scheduling circuit design | Michael Alexander | 2020-12-08 |
| 10860775 | Clock pin to clock tap assignment based on circuit device connectivity | Wing-Kai Chow | 2020-12-08 |
| 10796066 | Power aware resizing of clock tree instances | Amin Farshidi | 2020-10-06 |
| 10796049 | Waveform propagation timing modeling for circuit design | Kwangsoo Han, Charles J. Alpert | 2020-10-06 |
| 10769345 | Clock tree optimization by moving instances toward core route | Andrew Mark Chapman | 2020-09-08 |
| 10755024 | System and method for routing in an integrated circuit design | Wing-Kai Chow, Mehmet Can Yildiz | 2020-08-25 |
| 10740532 | Route driven placement of fan-out clock drivers | William Robert Reece, Thomas Andrew Newton | 2020-08-11 |
| 10740530 | Clock tree wirelength reduction based on a target offset in connected routes | Andrew Mark Chapman | 2020-08-11 |
| 10706202 | Devices and methods for balanced routing tree structures | Dirk Meyer | 2020-07-07 |
| 10685164 | Circuit design routing based on parallel run length rules | Yi-Xiao Ding, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz | 2020-06-16 |
| 10679120 | Power driven synaptic network synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Dharmendra S. Modha, Gi-Joon Nam | 2020-06-09 |
| 10643019 | View pruning for routing tree optimization | Kwangsoo Han, Charles J. Alpert | 2020-05-05 |
| 10643014 | Irregular sink arrangement for balanced routing tree structures | Dirk Meyer | 2020-05-05 |
| 10614261 | Honoring pin insertion delay during clock tree synthesis | Michael Alexander, Kwangsoo Han | 2020-04-07 |
| 10579767 | Systems and methods for routing a clock net with multiple layer ranges | Wen-Hao Liu, Gracieli Posser, Charles J. Alpert, Ruth Patricia Jackson | 2020-03-03 |