Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
SQ

Stephen T. Quay

IBM: 35 patents #2,774 of 70,183Top 4%
IBInternational Business: 1 patents #4 of 119Top 4%
Texas: #2,932 of 125,132 inventorsTop 3%
Overall (All Time): #94,242 of 4,157,543Top 3%
36 Patents All Time

Issued Patents All Time

Showing 26–36 of 36 patents

Patent #TitleCo-InventorsDate
6915496 Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique Charles J. Alpert, Chong-Nuen Chu, Rama Gopal Gandham, Milos Hrkic, Jiang Hu +1 more 2005-07-05
6898774 Buffer insertion with adaptive blockage avoidance Charles J. Alpert, Rama Gopal Gandham, Jiang Hu 2005-05-24
6591411 Apparatus and method for determining buffered steiner trees for complex circuits Charles J. Alpert, Rama Gopal Gandham, Jiang Hu, Andrew J. Sullivan 2003-07-08
6560752 Apparatus and method for buffer library selection for use in buffer insertion Charles J. Alpert, Rama Gopal Gandham, Jose L. Neves 2003-05-06
6401234 Method and system for re-routing interconnects within an integrated circuit design having blockages and bays Charles J. Alpert, Rama Gopal Gandham, Jiang Hu, Jose L. Neves 2002-06-04
6360350 Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms Carol Ivash Gabele, Paul G. Villarrubia, Parsotam T. Patel, Jean-Paul Watson 2002-03-19
6347393 Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation Charles J. Alpert, Anirudh Devgan 2002-02-12
6230302 Method and system for performing timing analysis on an integrated circuit design Carol Ivash Gabele, Paul G. Villarrubia, Parsotam T. Patel, Alexander K. Spencer 2001-05-08
6117182 Optimum buffer placement for noise avoidance Charles J. Alpert, Anirudh Devgan 2000-09-12
6044209 Method and system for segmenting wires prior to buffer insertion Charles J. Alpert, Anirudh Devgan 2000-03-28
5991521 Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure Carol Ivash Gabele, Clay Chip Smith 1999-11-23