Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9684751 | Slack redistribution for additional power recovery | Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha +1 more | 2017-06-20 |
| 9672322 | Virtual positive slack in physical synthesis | Kaustav Guha, Lakshmi N. Reddy, Sourav Saha | 2017-06-06 |
| 9672321 | Virtual positive slack in physical synthesis | Kaustav Guha, Lakshmi N. Reddy, Sourav Saha | 2017-06-06 |
| 9659140 | Critical region identification | George Antony, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Sourav Saha, Vinay K. Singh | 2017-05-23 |
| 9552451 | Cross-hierarchy interconnect adjustment for power recovery | Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha | 2017-01-24 |
| 9514265 | Congestion aware layer promotion | Lakshmi N. Reddy, Sourav Saha | 2016-12-06 |
| 9495502 | Congestion aware layer promotion | Lakshmi N. Reddy, Sourav Saha | 2016-11-15 |
| 9443047 | Physical aware technology mapping in synthesis | Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha | 2016-09-13 |
| 9443048 | Physical aware technology mapping in synthesis | Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha | 2016-09-13 |
| 9378326 | Critical region identification | George Antony, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Sourav Saha, Vinay K. Singh | 2016-06-28 |
| 8799846 | Facilitating the design of a clock grid in an integrated circuit | Joseph N. Kozhaya, Daniel R. Menard, Susan R. Sanicky, Amanda Christine Venton, Paul G. Villarrubia +1 more | 2014-08-05 |
| 8261224 | Computer program product, apparatus, and method for inserting components in a hierarchical chip design | Frank Malgioglio | 2012-09-04 |
| 8006213 | Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew | Jose L. Neves, Charlie C. Hwang, David W. Lewis | 2011-08-23 |
| 7987400 | Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy | Lawrence D. Curley, Patrick J. Meaney, Diana L. Orf | 2011-07-26 |
| 7979838 | Method of automating creation of a clock control distribution network in an integrated circuit floorplan | Jose L. Neves, Lawrence D. Curley, Patrick J. Meaney, Travis W. Pouarz, William J. Scarpero, Jr. | 2011-07-12 |
| 7921399 | Method for simplifying tie net modeling for router performance | Michael Alexander Bowen | 2011-04-05 |
| 7882322 | Early directory access of a double data rate elastic interface | Jonathan Y. Chen, Michael Fee, Patrick J. Meaney, Alan P. Wagstaff | 2011-02-01 |
| 7827513 | Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs | Joseph J. Palumbo, Adam R. Jalkowski | 2010-11-02 |
| 7752475 | Late data launch for a double data rate elastic interface | Jonathan Y. Chen, Michael Fee, Patrick J. Meaney, Alan P. Wagstaff | 2010-07-06 |
| 7739538 | Double data rate chaining for synchronous DDR interfaces | Michael Fee, Patrick J. Meaney, Jonathan Y. Chen, Alan P. Wagstaff | 2010-06-15 |
| 7735051 | Method for replicating and synchronizing a plurality of physical instances with a logical master | Gary A. Van Huben, David A. Webber | 2010-06-08 |
| 7681169 | Process for managing complex pre-wired net segments in a VLSI design | Michael Alexander Bowen, Michael R. Scheuermann, Michael H. Wood | 2010-03-16 |
| 7469399 | Semi-flattened pin optimization process for hierarchical physical designs | Christopher M. Carney, David L. Rude, Eddy St. Juste | 2008-12-23 |
| 7346877 | Decoupling capacitance analysis method | Howard H. Smith, Richard Paul Underwood, Alan P. Wagstaff | 2008-03-18 |
| 7269806 | Decoupling capacitance analysis method | Howard H. Smith, Richard Paul Underwood, Alan P. Wagstaff | 2007-09-11 |