| 12399735 |
Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests |
Andrew David Tune, Daniel Sara |
2025-08-26 |
| 12099456 |
Command processing circuitry maintaining a linked list defining entries for one or more command queues and executing synchronization commands at the queue head of the one or more command queues in list order based on completion criteria of the synchronization command at the head of a given command queue |
Andrew Brookfield Swaine |
2024-09-24 |
| 11314675 |
Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols |
Andrew David Tune, Daniel Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal |
2022-04-26 |
| 11281403 |
Circuitry and method |
Thomas Gaertner, Viswanath Chakrala |
2022-03-22 |
| 10771194 |
Interconnection network for integrated circuit |
Andrew David Tune, Zheng Xu |
2020-09-08 |
| 10761561 |
Error checking for primary signal transmitted between first and second clock domains |
Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Julian Jose Hilgemberg Pontes |
2020-09-01 |
| 10579469 |
Interconnection network for integrated circuit |
Andrew David Tune |
2020-03-03 |
| 10489323 |
Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave |
Andrew David Tune, Daniel Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal |
2019-11-26 |
| 9906440 |
Arbitrating and multiplexing circuitry |
Rakesh Raman, Andrew David Tune |
2018-02-27 |