Issued Patents All Time
Showing 1–25 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405898 | Memory synchronisation subsequent to a page table walk | . ABHISHEK RAJA, Alexander Donald Charles Chadwick, Timothy Hayes | 2025-09-02 |
| 12271320 | Apparatus and method using plurality of physical address spaces | Jason Parker, Yuval Elad, Martin Weidmann | 2025-04-08 |
| 12164425 | Technique for tracking modification of content of regions of memory | Olof Henrik Uhrenholt | 2024-12-10 |
| 12164436 | Apparatus and methods for setting indicator data to indicate whether a group of contiguously addressed information entries in a selected address information table provides a base address indicating a location within a contiguously address region comprising multiple address information tables at a later table level | — | 2024-12-10 |
| 12099456 | Command processing circuitry maintaining a linked list defining entries for one or more command queues and executing synchronization commands at the queue head of the one or more command queues in list order based on completion criteria of the synchronization command at the head of a given command queue | Guanghui Geng | 2024-09-24 |
| 12067263 | Controlling memory access in a data processing systems with multiple subsystems | Thomas Christopher Grocutt, Alexander Donald Charles Chadwick | 2024-08-20 |
| 12056058 | Cache replacement control | Andrew David Tune | 2024-08-06 |
| 11954048 | Variable nesting control parameter for table structure providing access control information for controlling access to a memory system | Jason Parker, Yuval Elad, Alexander Donald Charles Chadwick, Carlos Garcia-Tobin | 2024-04-09 |
| 11934320 | Translation lookaside buffer invalidation | — | 2024-03-19 |
| 11853226 | Address translation cache with use of page size information to select an invalidation lookup mode, or use of leaf-and-intermediate exclusive range-specifying invalidation request, or use of invalidation request specifying single address and page size information | — | 2023-12-26 |
| 11755497 | Memory management | — | 2023-09-12 |
| 11734440 | Memory access transaction with security check indication | — | 2023-08-22 |
| 11615022 | Apparatus and method for handling accesses targeting a memory | Lorenzo Di Gregorio | 2023-03-28 |
| 11614985 | Insert operation | Alexander Donald Charles Chadwick, Gareth James Street Evans, Jonathan Curtis Beard | 2023-03-28 |
| 11586554 | Cache arrangements for data processing systems | Olof Henrik Uhrenholt | 2023-02-21 |
| 11531624 | Address translation in a data processing apparatus | Viswanath Chakrala | 2022-12-20 |
| 11526443 | Read-if-hit-pre-PoPA request | Alexander Alfred Hornung | 2022-12-13 |
| 11507515 | Memory management unit with address translation cache | — | 2022-11-22 |
| 11379152 | Epoch-based determination of completion of barrier termination command | Peter Andrew Riocreux | 2022-07-05 |
| 11204879 | Memory management circuitry managing data transactions and address translations between an upstream device and a downstream device | — | 2021-12-21 |
| 10733111 | Memory management | Jason Parker | 2020-08-04 |
| 10664400 | Address translation cache partitioning | — | 2020-05-26 |
| 10664399 | Filtering coherency protocol transactions | Hakan Persson, Ian Rudolf Bratt, Bruce James Mathewson | 2020-05-26 |
| 10628355 | Apparatus and method for processing burst read transactions | Jamshed Jalal, Tushar P. Ringe, Anitha Kona, Michael Andrew Campbell | 2020-04-21 |
| 10621128 | Controlling transitions of devices between normal state and quiescent state | Dominic William Brown, Christopher Vincent Severino, Ashley John Crawford | 2020-04-14 |