Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9958932 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | David Williamson, James Nolan Hardage, Richard F. Russo | 2018-05-01 |
| 9898071 | Processor including multiple dissimilar processor cores | David Williamson | 2018-02-20 |
| 9852084 | Access permissions modification | Peter G. Soderquist, Pradeep Kanapathipillai, Bernard J. Semeria, Joshua P. de Cesare, David Williamson | 2017-12-26 |
| 9626185 | IT instruction pre-decode | Shyam Sundar, Ian D. Kountanis, Conrado Blasco-Allue, Wei-Han Lien, Ramesh Gunna | 2017-04-18 |
| 9600289 | Load-store dependency predictor PC hashing | Stephan G. Meier, John H. Mylius, Suparn Vats | 2017-03-21 |
| 9582276 | Processor and method for implementing barrier operation using speculative and architectural color values | Stephan G. Meier | 2017-02-28 |
| 9575754 | Zero cycle move | James B. Keller, John H. Mylius, Conrado Blasco-Allue, Suparn Vats | 2017-02-21 |
| 9563575 | Least recently used mechanism for cache line eviction from a cache memory | Brian P. Lilly, Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan, Prashant Jain | 2017-02-07 |
| 9430243 | Optimizing register initialization operations | James B. Keller, John H. Mylius, Conrado Blasco-Allue | 2016-08-30 |
| 9418010 | Global maintenance command protocol in a cache coherent system | Stephan G. Meier | 2016-08-16 |
| 9383806 | Multi-core processor instruction throttling | Wei-Han Lien, Rohit Kumar, Sandeep Gupta, Suresh Periyacheri, Shih-Chieh Wen | 2016-07-05 |
| 9336003 | Multi-level dispatch for a superscalar processor | John H. Mylius, Shyam Balasubramanian, Conrado Blasco-Allue | 2016-05-10 |
| 9317285 | Instruction set architecture mode dependent sub-size access of register with associated status indication | Sandeep Gupta, Conrado Blasco-Allue, John H. Mylius, James B. Keller | 2016-04-19 |
| 9311100 | Usefulness indication for indirect branch prediction training | Sandeep Gupta, Shyam Sundar, Wei-Han Lien, Conrado Blasco-Allue | 2016-04-12 |
| 9280471 | Mechanism for sharing private caches in a SoC | Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Wei-Han Lien, Sukalpa Biswas +2 more | 2016-03-08 |
| 9223577 | Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage | John H. Mylius, James B. Keller, Fang Liu, Shyam Sundar | 2015-12-29 |
| 9201658 | Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries | Ian D. Kountanis, James B. Keller | 2015-12-01 |
| 9176879 | Least recently used mechanism for cache line eviction from a cache memory | Brian P. Lilly, Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Hari Kannan, Prashant Jain | 2015-11-03 |
| 9128725 | Load-store dependency predictor content management | Stephan G. Meier, John H. Mylius, Suparn Vats | 2015-09-08 |
| 9128857 | Flush engine | Brian P. Lilly | 2015-09-08 |
| 9098418 | Coordinated prefetching based on training in hierarchically cached processors | Hari Kannan, Brian P. Lilly, Mahnaz Sadoughi-Yarandi, Perumal R. Subramoniam, Pradeep Kanapathipillai | 2015-08-04 |
| 9043554 | Cache policies for uncacheable memory requests | Brian P. Lilly, Perumal R. Subramoniam, Pradeep Kanapathipillai | 2015-05-26 |
| 9015422 | Access map-pattern match based prefetch unit for a processor | Stephan G. Meier, Hari Kannan, Pavlos Konas | 2015-04-21 |
| 8856447 | Converting memory accesses near barriers into prefetches | — | 2014-10-07 |
| 8775757 | Trust zone support in system on a chip having security enclave processor | R. Stephen Polzin, James B. Keller | 2014-07-08 |