Tony L. Werner — 20 Patents at Intel

Tony L. Werner has been granted 20 US patents while listed as an inventor at Intel. The first was granted in 2002 and the most recent in February 2025. Tony L. Werner ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Tony L. Werner in Los Altos, CA, US.

Patents per Year

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12229560	Multi-variate strided read operations for accessing matrix operands	Nitin N. Garegrat, Jeff DelChiaro, Michael Rotzin, Robert T. Rhoades, Ujwal Basavaraj Sajjanar +1 more	2025-02-18
11748625	Distributed convolution for neural networks	Vijay Anand R. Korthikanti, Aravind Kalaiah, Carey K. Kloss, Amir Khosrowshahi	2023-09-05	$19,899,000
11687341	Multi-variate strided read operations for accessing matrix operands	Nitin N. Garegrat, Jeff DelChiaro, Michael Rotzin, Robert T. Rhoades, Ujwal Basavaraj Sajjanar +1 more	2023-06-27	$18,721,000
10949496	Dimension shuffling using matrix processors	Vijay Anand R. Korthikanti, Aravind Kalaiah, Amir Khosrowshahi	2021-03-16	$38,556,000
10896039	Programmable matrix processing engine	Aravind Kalaiah, Vijay Anand R. Korthikanti, Horace Lau	2021-01-19	$115,732,000
10761757	Apparatus and method for coherent, accelerated conversion between data representations	Krishnakumar Narayanan Nair, Andrew Yang, Michael Rotzin, Nitin N. Garegrat, Tom Schebye	2020-09-01	$24,773,000
10620951	Matrix multiplication acceleration of sparse matrices using column folding and squeezing	Omid Azizi, Guy Boudoukh, Andrew Yang, Michael Rotzin, Chen Koren +1 more	2020-04-14	$33,667,000
10482155	Winograd algorithm on a matrix processing architecture	Aravind Kalaiah	2019-11-19	$26,843,000
10228937	Programmable matrix processing engine	Aravind Kalaiah, Vijay Anand R. Korthikanti, Horace Lau	2019-03-12	$21,255,000
10198401	Max pooling in a matrix processing architecture	Horace Lau	2019-02-05	$24,217,000
9886418	Matrix operands for linear algebra operations	Andrew Yang, Carey K. Kloss, Prashant Arora, Naveen Gandham Rao, Amir Khosrowshahi	2018-02-06	$17,987,000
9886377	Pipelined convolutional operations for processing clusters	Aravind Kalaiah, Andrew Yang, Carey K. Kloss, Horace Lau, Naveen Gandham Rao +1 more	2018-02-06	$17,987,000
7408937	Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms	Earl T. Cohen	2008-08-05	$50,241,000
7159102	Branch control memory	Naohiko Irie	2007-01-02
6772325	Processor architecture and operation for exploiting improved branch control instruction	Naohiko Irie	2004-08-03	$175,000
6449712	Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions	Naohiko Irie, Chih-Jui Peng, Sebastian Haviuj Ziesler, Jackie Andrew Freeman, Sivaram Krishnan	2002-09-10	$166,000
6397296	Two-level instruction cache for embedded processors	—	2002-05-28	$184,000
6393523	Mechanism for invalidating instruction cache blocks in a pipeline processor	Chih-Jui Peng, Margaret Rose Gearty, Naohiko Irie	2002-05-21	$160,000
6389531	Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency	Naohiko Irle	2002-05-14	$143,000
6374348	Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction	Naohiko Irie	2002-04-16	$196,000

Tony L. Werner — 20 Patents

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