Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Two-level instruction cache for embedded processors

Two-level instruction cache for embedded processors

US Patent 6397296 · Granted May 28, 2002

Estimated economic value: $184,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-variate strided read operations for accessing matrix operands2025
Distributed convolution for neural networks2023
Multi-variate strided read operations for accessing matrix operands2023
Dimension shuffling using matrix processors2021
Programmable matrix processing engine2021
Apparatus and method for coherent, accelerated conversion between data represent2020
Matrix multiplication acceleration of sparse matrices using column folding and s2020
Winograd algorithm on a matrix processing architecture2019
Programmable matrix processing engine2019
Max pooling in a matrix processing architecture2019
Pipelined convolutional operations for processing clusters2018
Matrix operands for linear algebra operations2018