Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12130740 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2024-10-29 |
| 12039336 | Packed data element predication processors, methods, systems, and instructions | Bret L. Toll, Ronak Singhal, Mishali Naik | 2024-07-16 |
| 11442734 | Packed data element predication processors, methods, systems, and instructions | Bret L. Toll, Ronak Singhal, Mishali Naik | 2022-09-13 |
| 11294809 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2022-04-05 |
| 10963257 | Packed data element predication processors, methods, systems, and instructions | Bret L. Toll, Ronak Singhal, Mishali Naik | 2021-03-30 |
| 10430193 | Packed data element predication processors, methods, systems, and instructions | Bret L. Toll, Ronak Singhal, Mishali Naik | 2019-10-01 |
| 10282296 | Zeroing a cache line | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +5 more | 2019-05-07 |
| 10228941 | Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register | Bret L. Toll, Ronak Singhal, Mishali Naik | 2019-03-12 |
| 9990202 | Packed data element predication processors, methods, systems, and instructions | Bret L. Toll, Ronak Singhal, Mishali Naik | 2018-06-05 |
| 9934032 | Processors, methods, and systems to implement partial register accesses with masked full register accesses | Edward T. Grochowski, Seyed Yahya Sotoudeh | 2018-04-03 |
| 9477467 | Processors, methods, and systems to implement partial register accesses with masked full register accesses | Edward T. Grochowski, Seyed Yahya Sotoudeh | 2016-10-25 |