Issued Patents All Time
Showing 26–50 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7437724 | Registers for data transfers | Gilbert M. Wolrich, Mark Rosenbluth, Matthew J. Adiletta, Hugh Wilkinson | 2008-10-14 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register | Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Donald F. Hooper | 2008-09-02 |
| 7418540 | Memory controller with command queue look-ahead | Natarajan Rohit, Gilbert M. Wolrich, Chang-Ming Lin | 2008-08-26 |
| 7418543 | Processor having content addressable memory with command ordering | Sanjeev Kumar Jain, Gilbert M. Wolrich | 2008-08-26 |
| 7376950 | Signal aggregation | Gilbert M. Wolrich, Mark Rosenbluth, Myles Wilde | 2008-05-20 |
| 7366865 | Enqueueing entries in a packet queue referencing packets | Sridhar Lakshmanamurthy, Sanjeev Kumar Jain, Gilbert M. Wolrich | 2008-04-29 |
| 7337275 | Free list and ring data structure management | Gilbert M. Wolrich, Mark Rosenbluth, John Sweeney, James D. Guilford | 2008-02-26 |
| 7328289 | Communication between processors | Gilbert M. Wolrich, Matthew J. Adiletta | 2008-02-05 |
| 7324520 | Method and apparatus to process switch traffic | Sridhar Lakshmanamurthy, Lawrence B. Huston, III, Hugh Wilkinson, Mark Rosenbluth | 2008-01-29 |
| 7313140 | Method and apparatus to assemble data segments into full packets for efficient packet-based classification | Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, III, Yim Pun, Raymond Ng +1 more | 2007-12-25 |
| 7302549 | Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access | Hugh Wilkinson, Matthew J. Adiletta, Gilbert M. Wolrich, Mark Rosenbluth, Myles Wilde | 2007-11-27 |
| 7269179 | Control mechanisms for enqueue and dequeue operations in a pipelined network processor | Gilbert M. Wolrich, Mark Rosenbluth, Matthew J. Adiletta | 2007-09-11 |
| 7246197 | Software controlled content addressable memory in a general purpose execution datapath | Mark Rosenbluth, Gilbert M. Wolrich | 2007-07-17 |
| 7240164 | Folding for a multi-threaded network processor | Donald F. Hooper, Hugh Wilkinson, Mark Rosenbluth, Michael F. Fallon, Sanjeev Kumar Jain +2 more | 2007-07-03 |
| 7225281 | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms | Mark Rosenbluth, Gilbert M. Wolrich, Myles Wilde, Matthew J. Adiletta | 2007-05-29 |
| 7216204 | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment | Mark Rosenbluth, Gilbert M. Wolrich | 2007-05-08 |
| 7191321 | Microengine for parallel processor architecture | Donald F. Hooper, Matthew J. Adiletta, Gilbert M. Wolrich, William R. Wheeler | 2007-03-13 |
| 7191309 | Double shift instruction for micro engine used in multithreaded parallel processor architecture | Gilbert M. Wolrich, Matthew Adiletta, William R. Wheeler, Donald F. Hooper | 2007-03-13 |
| 7181594 | Context pipelines | Hugh Wilkinson, Mark Rosenbluth, Matthew J. Adiletta, Gilbert M. Wolrich | 2007-02-20 |
| 7181573 | Queue array caching in network devices | Gilbert M. Wolrich, Mark Rosenbluth | 2007-02-20 |
| 7158964 | Queue management | Gilbert M. Wolrich, Mark Rosenbluth, Donald F. Hooper | 2007-01-02 |
| 7149226 | Processing data packets | Gilbert M. Wolrich, Mark Rosenbluth | 2006-12-12 |
| 7111296 | Thread signaling in multi-threaded processor | Gilbert M. Wolrich, Donald F. Hooper, Matthew J. Adiletta, William R. Wheeler | 2006-09-19 |
| 7107413 | Write queue descriptor count instruction for high speed queuing | Mark Rosenbluth, Gilbert M. Wolrich | 2006-09-12 |
| 7020871 | Breakpoint method for parallel hardware threads in multithreaded processor | Serge Kornfeld, Desmond R. Johnson, Donald F. Hooper, James D. Guilford, Richard Muratori | 2006-03-28 |