Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6976095 | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch | Gilbert M. Wolrich, Matthew J. Adiletta | 2005-12-13 |
| 6973550 | Memory access control | Mark Rosenbluth, Gilbert M. Wolrich, Richard Guerin | 2005-12-06 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section | Hugh Wilkinson, Matthew J. Adiletta, Gilbert M. Wolrich, Mark Rosenbluth, Myles Wilde | 2005-08-23 |
| 6895457 | Bus interface with a first-in-first-out memory | Gilbert M. Wolrich, Matthew J. Adiletta | 2005-05-17 |
| 6876561 | Scratchpad memory | Gilbert M. Wolrich, Matthew J. Adiletta | 2005-04-05 |
| 6868476 | Software controlled content addressable memory in a general purpose execution datapath | Mark Rosenbluth, Gilbert M. Wolrich | 2005-03-15 |
| 6792488 | Communication between processors | Gilbert M. Wolrich, Matthew J. Adiletta | 2004-09-14 |
| 6779084 | Enqueue operations for multi-buffer packets | Gilbert M. Wolrich, Mark Rosenbluth | 2004-08-17 |
| 6738831 | Command ordering | Gilbert M. Wolrich, Mark Rosenbluth, Richard Guerin | 2004-05-18 |
| 6694380 | Mapping requests from a processing unit that uses memory-mapped input-output space | Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta | 2004-02-17 |
| 6681300 | Read lock miss control and queue management | Gilbert M. Wolrich, Daniel Cutter, William R. Wheeler, Matthew J. Adiletta | 2004-01-20 |
| 6668317 | Microengine for parallel processor architecture | Donald F. Hooper, Matthew J. Adiletta, Gilbert M. Wolrich, William R. Wheeler | 2003-12-23 |
| 6667920 | Scratchpad memory | Gilbert M. Wolrich, Matthew J. Adiletta | 2003-12-23 |
| 6661794 | Method and apparatus for gigabit packet assignment for multithreaded packet processing | Gilbert M. Wolrich, Matthew J. Adiletta, Donald F. Hooper | 2003-12-09 |
| 6631430 | Optimizations to receive packet status from fifo bus | Gilbert M. Wolrich, Matthew J. Adiletta | 2003-10-07 |
| 6631462 | Memory shared between processing threads | Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Daniel Cutter | 2003-10-07 |
| 6625654 | Thread signaling in multi-threaded network processor | Gilbert M. Wolrich, Donald F. Hooper, Matthew J. Adiletta, William R. Wheeler | 2003-09-23 |
| 6587906 | Parallel multi-threaded processing | Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler | 2003-07-01 |
| 6584522 | Communication between processors | Gilbert M. Wolrich, Matthew J. Adiletta | 2003-06-24 |
| 6577542 | Scratchpad memory | Gilbert M. Wolrich, Matthew J. Adiletta | 2003-06-10 |
| 6560667 | Handling contiguous memory references in a multi-queue system | Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler | 2003-05-06 |
| 6532509 | Arbitrating command requests in a parallel multi-threaded processing system | Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler | 2003-03-11 |
| 6463072 | Method and apparatus for sharing access to a bus | Gilbert M. Wolrich, Matthew J. Adiletta | 2002-10-08 |
| 6324624 | Read lock miss control and queue management | Gilbert M. Wolrich, Daniel Cutter, William R. Wheeler, Matthew J. Adiletta | 2001-11-27 |
| 6307789 | Scratchpad memory | Gilbert M. Wolrich, Matthew J. Adiletta | 2001-10-23 |