Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417121 | Memory pool management | Francois Dugast, Florent Pirou, Sujoy Sen, Lidia Warnes, Thomas E. Willis | 2025-09-16 |
| 12381751 | Direct memory access (DMA) engine with network interface capabilities | Sujoy Sen, Thomas E. Willis, Bassam N. Coury, Marcelo Cintra | 2025-08-05 |
| 12373335 | Memory thin provisioning using memory pools | Debra Bernstein, Hugh Wilkinson, Douglas Carrigan, Bassam N. Coury, Matthew J. Adiletta +3 more | 2025-07-29 |
| 12375390 | Memory pooled time sensitive networking based architectures | Francois Dugast, Francesc Guim Bernat, Karthik Kumar | 2025-07-29 |
| 12192024 | Shared memory | Bassam N. Coury, Sujoy Sen, Thomas E. Willis | 2025-01-07 |
| 12192023 | Page-based remote memory access using system memory interface network device | Sujoy Sen, Thomas E. Willis, Bassam N. Coury, Marcelo Cintra | 2025-01-07 |
| 12132581 | Network interface controller with eviction cache | Sujoy Sen, Thomas E. Willis, Bassam N. Coury, Marcelo Cintra | 2024-10-29 |
| 12086446 | Memory and storage pool interfaces | Sujoy Sen, Thomas E. Willis, Marcelo Cintra, Bassam N. Coury, Donald L. Faw +1 more | 2024-09-10 |
| 11983408 | Ballooning for multi-tiered pooled memory | Rasika Subramanian, Lidia Warnes, Francesc Guim Bernat, Mark A. Schmisseur | 2024-05-14 |
| 11726565 | Context aware selective backlighting techniques | Dhaval V. Sharma, Nivruti Rai, Shobhit Kumar | 2023-08-15 |
| 11681439 | Ballooning for multi-tiered pooled memory | Rasika Subramanian, Lidia Warnes, Francesc Guim Bernat, Mark A. Schmisseur | 2023-06-20 |
| 11573722 | Tenant based allocation for pooled memory | Rasika Subramanian, Lidia Warnes, Francesc Guim Bernat, Mark A. Schmisseur | 2023-02-07 |
| 11397464 | Context aware selective backlighting techniques | Dhaval V. Sharma, Nivruti Rai, Shobhit Kumar | 2022-07-26 |
| 10976815 | Context aware selective backlighting techniques | Dhaval V. Sharma, Nivruti Rai, Shobhit Kumar | 2021-04-13 |
| 10324525 | Context aware selective backlighting techniques | Dhaval V. Sharma, Nivruti Rai, Shobhit Kumar | 2019-06-18 |
| 9229895 | Multi-core integrated circuit configurable to provide multiple logical domains | James A. Coleman, Gerald Rogers, Scott M. Oehrlein | 2016-01-05 |
| 8091000 | Disabling portions of memory with defects | Tsung-Yung Chang, Jonathan Shoemaker, John Benoit | 2012-01-03 |
| 8024594 | Method and apparatus for reducing power consumption in multi-channel memory controller systems | Yean Kee Yong, Niall D. McDonnell, Rakesh Dodeja, Neelam Chandwani | 2011-09-20 |
| 7861053 | Supporting un-buffered memory modules on a platform configured for registered memory modules | Kok Lye Wah, Sivakumar Murugesu, Ooi Ping Chuin | 2010-12-28 |
| 7836458 | Configuration system | Kazimierz Krzysztof Gwozdz, Marcus J. Jager | 2010-11-16 |
| 7725757 | Method and system for fast frequency switch for a power throttle in an integrated device | Kiran Padweka, Arvind Mandhani | 2010-05-25 |
| 7571341 | Method and system for fast frequency switch for a power throttle in an integrated device | Kiran Padwekar, Arvind Mandhani | 2009-08-04 |
| 7555597 | Direct cache access in multiple core processors | Jeffrey D. Gilbert | 2009-06-30 |
| 7475269 | Method and system for fast frequency switch for a power throttle in an integrated device | Kiran Padwekar, Arvind Mandhani | 2009-01-06 |
| 7418461 | Schema conformance for database servers | Leela S. Tamma, Krishna Vitaldevara | 2008-08-26 |