Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Kiran Padwekar — 14 Patents

Intel: 13 patents #3,167 of 30,777Top 15%
Santa Clara, CA: #1,234 of 9,301 inventorsTop 15%
California: #43,920 of 386,348 inventorsTop 15%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Kiran Padwekar has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 1997 and the most recent in August 2017. Kiran Padwekar ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Kiran Padwekar in Santa Clara, CA, US.

Patents per Year

Patents granted per year, 1997 to 2017Bar chart with a peak of 3 patents in 2006.peak 31997: 1 patents19971999: 1 patents2000: 1 patents20002001: 1 patents2003: 1 patents20032005: 1 patents2006: 3 patents20062007: 1 patents2009: 2 patents20092011: 1 patents2017: 1 patents2017

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9729309 Securing data transmission between processor packages Simon P. Johnson, Abhishek Das, Carlos V. Rozas, Uday Savagaonkar, Robert G. Blankenship 2017-08-08 $11,912,000
7991875 Link level retry scheme Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava +3 more 2011-08-02 $15,238,000
7571341 Method and system for fast frequency switch for a power throttle in an integrated device Arvind Mandhani, Durgesh Srivastava 2009-08-04 $15,097,000
7475269 Method and system for fast frequency switch for a power throttle in an integrated device Arvind Mandhani, Durgesh Srivastava 2009-01-06 $21,219,000
7272736 Method and system for fast frequency switch for a power throttle in an integrated device Arvind Mandhani, Durgesh Srivastava 2007-09-18 $14,997,000
7107437 Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB) 2006-09-12 $13,412,000
7100027 System and method for reproducing system executions using a replay handler 2006-08-29 $13,270,000
7016304 Link level retry scheme Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava +3 more 2006-03-21 $17,683,000
6925584 Systems and methods for testing processors Jesse Pan, Sudhakar Bhat 2005-08-02 $20,766,000
6571359 Systems and methods for testing processors Jesse Pan, Sudhakar Bhat 2003-05-27 $49,574,000
6317822 Instruction encoding techniques for microcontroller architecture 2001-11-13 $122,229,000
6154833 System for recovering from a concurrent branch target buffer read with a write allocation by invalidating and then reinstating the instruction pointer Keshavram N. Murty, James A. Stone 2000-11-28 $170,940,000
5897665 Register addressing for register-register architectures used for microprocessors and microcontrollers 1999-04-27 $99,695,000
5652847 Circuit and system for multiplexing data and a portion of an address on a bus 1997-07-29