Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9729309 | Securing data transmission between processor packages | Simon P. Johnson, Abhishek Das, Carlos V. Rozas, Uday Savagaonkar, Robert G. Blankenship | 2017-08-08 |
| 7991875 | Link level retry scheme | Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava +3 more | 2011-08-02 |
| 7571341 | Method and system for fast frequency switch for a power throttle in an integrated device | Arvind Mandhani, Durgesh Srivastava | 2009-08-04 |
| 7475269 | Method and system for fast frequency switch for a power throttle in an integrated device | Arvind Mandhani, Durgesh Srivastava | 2009-01-06 |
| 7272736 | Method and system for fast frequency switch for a power throttle in an integrated device | Arvind Mandhani, Durgesh Srivastava | 2007-09-18 |
| 7107437 | Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB) | — | 2006-09-12 |
| 7100027 | System and method for reproducing system executions using a replay handler | — | 2006-08-29 |
| 7016304 | Link level retry scheme | Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava +3 more | 2006-03-21 |
| 6925584 | Systems and methods for testing processors | Jesse Pan, Sudhakar Bhat | 2005-08-02 |
| 6571359 | Systems and methods for testing processors | Jesse Pan, Sudhakar Bhat | 2003-05-27 |
| 6317822 | Instruction encoding techniques for microcontroller architecture | — | 2001-11-13 |
| 6154833 | System for recovering from a concurrent branch target buffer read with a write allocation by invalidating and then reinstating the instruction pointer | Keshavram N. Murty, James A. Stone | 2000-11-28 |
| 5897665 | Register addressing for register-register architectures used for microprocessors and microcontrollers | — | 1999-04-27 |
| 5652847 | Circuit and system for multiplexing data and a portion of an address on a bus | — | 1997-07-29 |