Issued Patents All Time
Showing 51–60 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5222223 | Method and apparatus for ordering and queueing multiple memory requests | David A. Webb, John E. Murray, Tryggve Fossum, Dwight P. Manley | 1993-06-22 |
| 5222224 | Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system | Michael Flynn, Scott Arnold, Stephen J. DeLaHunt, Tryggve Fossum, David J. Webb | 1993-06-22 |
| 5142631 | System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register | John E. Murray, Mark A. Firstenberg, David B. Fite, Jr., Michael M. McKeon, Wiliam R. Grundmann +4 more | 1992-08-25 |
| 5125083 | Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system | David B. Fite, Jr., Tryggve Fossum, John E. Murray, Jr. David A. Webb | 1992-06-23 |
| 5113515 | Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer | David B. Fite, Jr., Michael M. McKeon, Dwight P. Manley, John E. Murray | 1992-05-12 |
| 5019965 | Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width | David A. Webb, Ronald M. Salett, Trvggve Fossum, Dwight P. Manley | 1991-05-28 |
| 4995041 | Write back buffer with error correcting capabilities | Tryggve Fossum, Maurice B. Steinman, David A. Webb | 1991-02-19 |
| 4985825 | System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer | David A. Webb, David B. Fite, Jr., Francis X. McKeen, Mark A. Firstenberg, John E. Murray +3 more | 1991-01-15 |
| 4982402 | Method and apparatus for detecting and correcting errors in a pipelined computer system | Richard C. Beaven, Michael B. Evans, Tryggve Fossum, William R. Grundmann, John E. Murray +1 more | 1991-01-01 |
| 4888679 | Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements | Tryggve Fossum, David B. Fite, Jr., Dwight P. Manley, Francis X. McKeen, John E. Murray | 1989-12-19 |