Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Sharath Raghava — 13 Patents

Intel: 7 patents #5,443 of 30,777Top 20%
NVIDIA: 4 patents #1,739 of 7,811Top 25%
LSLattice Semiconductor: 1 patents #317 of 544Top 60%
Oracle: 1 patents #8,339 of 14,854Top 60%
San Jose, CA: #5,025 of 32,062 inventorsTop 20%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Sharath Raghava has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 2006 and the most recent in September 2025. Sharath Raghava ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Sharath Raghava in San Jose, CA, US.

Patents per Year

Patents granted per year, 2006 to 2025Bar chart with a peak of 3 patents in 2025.peak 32006: 1 patents20062016: 2 patents20162017: 2 patents20172020: 2 patents20202022: 1 patents20222023: 2 patents20232025: 3 patents2025

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12417319 Multi-chip secure and programmable systems and methods Srirama Chandra, Tim Vogt, Mamta Gupta 2025-09-16
12237831 Network-on-chip (NOC) with flexible data width Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad +1 more 2025-02-25
12204441 Flushing cache lines involving persistent memory Nagabhushan Chitlur, Harsha Gupta 2025-01-21
11789883 Inter-die communication of programmable logic devices Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta 2023-10-17 $15,641,000
11700002 Network-on-chip (NOC) with flexible data width Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad +1 more 2023-07-11 $21,736,000
11342918 Network-on-chip (NOC) with flexible data width Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad +1 more 2022-05-24 $18,289,000
10790827 Network-on-chip (NOC) with flexible data width Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad +1 more 2020-09-29 $31,444,000
10649927 Dual in-line memory module (DIMM) programmable accelerator card Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta 2020-05-12 $29,489,000
9824772 Hardware chip select training for memory using read commands Venkata Ramana Malladi, Tony Yuhsiang Cheng, Ambuj Kumar, Arunjit Sahni, Paul Lam 2017-11-21 $112,129,000
9607714 Hardware command training for memory using write leveling mechanism Venkata Ramana Malladi, Tony Yuhsiang Cheng, Ambuj Kumar, Arunjit Sahni, Paul Lam 2017-03-28 $166,161,000
9378169 Method and system for changing bus direction in memory systems Ambuj Kumar, Brian K. Langendorf, Tony Yuhsiang Cheng 2016-06-28 $37,849,000
9368169 Hardware chip select training for memory using write leveling mechanism Venkata Ramana Malladi, Tony Yuhsiang Cheng, Ambuj Kumar, Arunjit Sahni, Paul Lam 2016-06-14 $17,088,000
7143304 Method and apparatus for enhancing the speed of a synchronous bus Kevin Normoyle, Christopher Furman 2006-11-28 $10,042,000