Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 9619396 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu | 2017-04-11 |
| 9606925 | Method, apparatus and system for optimizing cache memory transaction handling in a processor | Bahaa Fahim, Yen-Cheng Liu, Jeffrey D. Chamberlain, Min Huang | 2017-03-28 |
| 9436605 | Cache coherency apparatus and method minimizing memory writeback operations | Jeffrey D. Chamberlain, Robert G. Blankenship, Yen-Cheng Liu, Adrian C. Moga, Herbert Hum +1 more | 2016-09-06 |
| 9418009 | Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory | Adrian C. Moga, Bahaa Fahim, Robert G. Blankenship, Yen-Cheng Liu, Jeffrey D. Chamberlain +1 more | 2016-08-16 |
| 9405687 | Method, apparatus and system for handling cache misses in a processor | Bahaa Fahim, Samuel D. Strom, Robert G. Blankenship, Yen-Cheng Liu, Krishnakumar Ganapathy +1 more | 2016-08-02 |
| 8631210 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Adrian C. Moga, Malcolm Mandviwalla, Herbert Hum | 2014-01-14 |
| 8495091 | Dynamically routing data responses directly to requesting processor core | Allen J. Baum, Sailesh Kottapalli | 2013-07-23 |
| 8392665 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Adrian C. Moga, Malcolm Mandviwalla, Herbert Hum | 2013-03-05 |