Issued Patents All Time
Showing 25 most recent of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393515 | Global persistent flush | — | 2025-08-19 |
| 12360934 | Parameter exchange for a die-to-die interconnect | Debendra Das Sharma, Sridhar Muthrasanallur, Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan | 2025-07-15 |
| 12314397 | Support of PCIe device with multiple security policies | Jiewen Yao, David J. Harriman, Xiaoyu Ruan | 2025-05-27 |
| 11954047 | Circuitry and methods for spatially unique and location independent persistent memory encryption | Anand K. Enamandram, Manjula Peddireddy, Robert A. Branch, Tiffany J. Kasanicky, Siddhartha Chhabra +1 more | 2024-04-09 |
| 11928059 | Host-managed coherent device memory | Vivekananthan Sanjeepan | 2024-03-12 |
| 11789889 | Mechanism for device interoperability of switches in computer buses | — | 2023-10-17 |
| 11741227 | Platform security mechanism | Michael Berger, Xiaoyu Ruan, Purushottam Goel, Bharat S. Pillilli | 2023-08-29 |
| 11704181 | Apparatus and method for scalable error detection and reporting | Balaji Vembu, Bryan R. White, Ankur N. Shah, Murali Ramadoss, David Puffer +2 more | 2023-07-18 |
| 11522679 | Exposing cryptographic measurements of peripheral component interconnect express (PCIe) device controller firmware | Adrian R. Pearson | 2022-12-06 |
| 11416397 | Global persistent flush | — | 2022-08-16 |
| 11385952 | Apparatus and method for scalable error detection and reporting | Balaji Vembu, Bryan R. White, Ankur N. Shah, Murali Ramadoss, David Puffer +2 more | 2022-07-12 |
| 11347643 | Control logic and methods to map host-managed device memory to a system address space | Vivekananthan Sanjeepan | 2022-05-31 |
| 11222119 | Technologies for secure and efficient native code invocation for firmware services | Sarathy Jayakumar, Mohan J. Kumar, Ron Story | 2022-01-11 |
| 11216404 | Mechanism for device interoperability of switches in computer buses | — | 2022-01-04 |
| 11048626 | Technology to ensure sufficient memory type range registers to fully cache complex memory configurations | Kerry B. Vander Kamp, Jason Voelz, James R. Goffena, Robert A. Branch, Anand K. Enamandram | 2021-06-29 |
| 10922161 | Apparatus and method for scalable error detection and reporting | Balaji Vembu, Bryan R. White, Ankur N. Shah, Murali Ramadoss, David Puffer +2 more | 2021-02-16 |
| 10810141 | Memory control management of a processor | Murugasamy K. Nachimuthu, Bill Nale | 2020-10-20 |
| 10802903 | Logging errors in error handling devices in a system | Sivakumar Radhakrishnan, Malay Trivedi, Jayasekhar Tholiyil, Erik A. McShane, Roger Liu | 2020-10-13 |
| 10691839 | Method, apparatus, and system for manageability and secure routing and endpoint access | Eric J. Dahlen | 2020-06-23 |
| 10671466 | Secure tunneling access to debug test ports on non-volatile memory storage units | Shamanna M. Datta, Murugasamy K. Nachimuthu | 2020-06-02 |
| 10671416 | Layered virtual machine integrity monitoring | Shamanna M. Datta | 2020-06-02 |
| 10379768 | Selective memory mode authorization enforcement | Vedaraman Geetha | 2019-08-13 |
| 10346177 | Boot process with parallel memory initialization | Wei-Pin Chen, Jing Ling, James E. McCormick, Jr. | 2019-07-09 |
| 10339047 | Allocating and configuring persistent memory | Scott W. Kirvan, Andy Rudoff, Murugasamy K. Nachimuthu | 2019-07-02 |
| 10324867 | Systems and devices having a scalable basic input/output system (BIOS) footprint and associated methods | Sivakumar Radhakrishnan, Zhenyu Zhu, Malay Trivedi, Randall L. Albion, Chris Ruffin | 2019-06-18 |