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Bharat S. Pillilli — 25 Patents

Intel: 15 patents #2,763 of 30,777Top 9%
Microsoft: 10 patents #4,378 of 40,388Top 15%
Park Village, CA: #25 of 95 inventorsTop 30%
California: #22,079 of 386,348 inventorsTop 6%
Overall (All Time): #158,593 of 4,157,543Top 4%
25 Patents All Time
Bharat S. Pillilli has been granted 25 US patents while listed as an inventor at Intel. The first was granted in 2014 and the most recent in December 2025. Bharat S. Pillilli ranks #158,593 of 4,157,543 US inventors in our database (top 3.8%). Patent records list Bharat S. Pillilli in Park Village, CA, US.

Issued Patents All Time

Showing 1–25 of 25 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12500736 Montgomery multiplier architecture Mojtaba Bisheh Niasar 2025-12-16
12476796 Cryptographic system real-time test vector leakage assessment Mojtaba Bisheh Niasar 2025-11-18
12470370 Hash based cryptography accelerator Mojtaba Bisheh Niasar 2025-11-11
12457092 Elliptic curve cryptography masked blinding countermeasure Mojtaba Bisheh Niasar 2025-10-28
12381742 Side channel attack resistant cryptographic accelerator Mojtaba Bisheh Niasar 2025-08-05
12299105 Partitioned platform security mechanism David W. Palmer, Nikola Radovanovic 2025-05-13
12273462 Low-cost, high-security solutions for digital signature algorithm Emre Karabulut, Mojtaba Bisheh Niasar 2025-04-08
12273446 Simplified masking for signed cryptography operations Emre Karabulut, Mojtaba Bisheh Niasar 2025-04-08
12259973 Systems and methods for flush plus reload cache side-channel attack mitigation Ishwar Agarwal, Vishal Soni 2025-03-25
12210649 Securing ATS from rogue devices for confidential computing Vishal Soni, Bryan Kelly 2025-01-28
12204912 Booting and using a single CPU socket as a multi-CPU partitioned platform Johan G. Van De Groenendaal 2025-01-21
12189457 Reducing latency of changing an operating state of a processor from a low-power state to a normal-power state Bryan Kelly 2025-01-07
12164907 Firmware update technologies Johan G. Van De Groenendaal 2024-12-10 $13,394,000
12045135 System and method for granular reset management without reboot Eswaramoorthi Nallusamy 2024-07-23 $20,446,000
11983260 Partitioned platform security mechanism David W. Palmer, Nikola Radovanovic 2024-05-14 $33,809,000
11940944 Fuse recipe update mechanism Saravana Priya Ramanathan, Reshma Lal 2024-03-26 $33,708,000
11803643 Boot code load system Eswaramoorthi Nallusamy 2023-10-31 $30,374,000
11741227 Platform security mechanism Michael Berger, Xiaoyu Ruan, Purushottam Goel, Mahesh S. Natu 2023-08-29 $19,273,000
11693940 Partitioned platform security mechanism David W. Palmer, Nikola Radovanovic 2023-07-04
11645159 System and method for granular reset management without reboot Eswaramoorthi Nallusamy 2023-05-09 $19,706,000
11494330 Fuse recipe update mechanism Saravana Priya Ramanathan, Reshma Lal 2022-11-08 $15,080,000
11157064 Techniques to dynamically enable and disable accelerator devices in compute environments Eswaramoorthi Nallusamy, Ramamurthy Krithivas, Vivek Garg, Venkatesh Ramamurthy 2021-10-26 $21,268,000
10761938 System and method for granular reset management without reboot Eswaramoorthi Nallusamy 2020-09-01 $24,773,000
10496298 Configurable flush of data from volatile memory to non-volatile memory Phani Kumar Kandula, Suresh Chemudupati, Yi-Feng Liu 2019-12-03 $19,496,000
8775990 Alignment of microarchitectural conditions Peter J. Smith, Harikrishna B. Baliga, Michael S. Yu, Shlomi Alkalay 2014-07-08 $15,420,000

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