Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6106573 | Apparatus and method for tracing microprocessor instructions | Rupaka Mahalingaiah | 2000-08-22 |
| 6101595 | Fetching instructions from an instruction cache using sequential way prediction | Thang M. Tran | 2000-08-08 |
| 6088781 | Stride instruction for fetching data separated by a stride amount | — | 2000-07-11 |
| 6079006 | Stride-based data address prediction structure | — | 2000-06-20 |
| 6076156 | Instruction redefinition using model specific registers | David S. Christie | 2000-06-13 |
| 6073230 | Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches | Thang M. Tran | 2000-06-06 |
| 6058461 | Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation | W. Kurt Lewchuk, Brian D. McMinn | 2000-05-02 |
| 5968169 | Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses | — | 1999-10-19 |
| 5958045 | Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor | — | 1999-09-28 |
| 5940876 | Stride instruction for fetching data separated by a stride amount | — | 1999-08-17 |
| 5933618 | Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction | Thang M. Tran, Rupaka Mahalingaiah | 1999-08-03 |
| 5933626 | Apparatus and method for tracing microprocessor instructions | Rupaka Mahalingaiah | 1999-08-03 |
| 5926646 | Context-dependent memory-mapped registers for transparent expansion of a register file | Rupaka Mahalingaiah, Brian D. McMinn | 1999-07-20 |
| 5892936 | Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register | Thang M. Tran, Rupaka Mahalingaiah | 1999-04-06 |
| 5893146 | Cache structure having a reduced tag comparison to enable data transfer from said cache | — | 1999-04-06 |
| 5872943 | Apparatus for aligning instructions using predecoded shift amounts | Thang M. Tran | 1999-02-16 |
| 5854921 | Stride-based data address prediction structure | — | 1998-12-29 |
| 5848433 | Way prediction unit and a method for operating the same | Thang M. Tran | 1998-12-08 |
| 5845323 | Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time | James Roberts | 1998-12-01 |
| 5832297 | Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations | H. S. Ramagopal, Thang M. Tran | 1998-11-03 |
| 5764946 | Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address | Thang M. Tran | 1998-06-09 |
| 5761712 | Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array | Thang M. Tran | 1998-06-02 |
| 5752069 | Superscalar microprocessor employing away prediction structure | James Roberts | 1998-05-12 |
| 5664167 | Microprogrammed timer processor having a variable loop resolution architecture | David W. Stringfellow | 1997-09-02 |
| 5339395 | Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode | Philip A. Inman, Matthew D. Sale | 1994-08-16 |