Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JR

James Roberts — 29 Patents

NVIDIA: 20 patents #308 of 7,811Top 4%
AMD: 9 patents #1,504 of 9,280Top 20%
Austin, TX: #1,056 of 18,064 inventorsTop 6%
Texas: #4,128 of 125,132 inventorsTop 4%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
James Roberts has been granted 29 US patents while listed as an inventor at NVIDIA. The first was granted in 1998 and the most recent in December 2019. James Roberts ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list James Roberts in Austin, TX, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10515011 Compression status bit cache and backing store David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2019-12-24
8949541 Techniques for evicting dirty data from a cache using a notification sorter and count thresholds David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, John H. Edmondson 2015-02-03 $4,737,000
8874844 Padding buffer requests to avoid reads of invalid data David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand 2014-10-28 $4,694,000
8868838 Multi-class data cache policies David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand 2014-10-21 $7,372,000
8862823 Compression status caching David B. Glasco, Cass W. Everitt, David Kirk McAllister, Emmett M. Kilgariff, George R. Lynch +4 more 2014-10-14 $3,953,000
8700862 Compression status bit cache and backing store David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2014-04-15 $1,804,000
8627041 Efficient line and page organization for compression status bit caching David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra +2 more 2014-01-07 $9,683,000
8595437 Compression status bit cache with deterministic isochronous latency David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2013-11-26 $5,902,000
8504773 Storing dynamically sized buffers within a cache David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand 2013-08-06 $5,004,000
8464001 Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism John H. Edmondson, David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand 2013-06-11 $6,924,000
8341358 System and method for cleaning dirty data in a cache via frame buffer logic John H. Edmondson 2012-12-25
8271734 Method and system for converting data formats using a shared cache coupled between clients and an external memory David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2012-09-18 $10,312,000
8244984 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, John H. Edmondson 2012-08-14 $7,609,000
8234478 Using a data cache array as a DRAM load/store buffer David B. Glasco, Patrick R. Marchand, Peter B. Holmqvist, George R. Lynch, John H. Edmondson 2012-07-31 $9,777,000
8156404 L2 ECC implementation David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2012-04-10 $18,398,000
8135926 Cache-based control of atomic operations in conjunction with an external ALU block David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2012-03-13 $7,465,000
8131931 Configurable cache occupancy policy David B. Glasco, Patrick R. Marchand, Peter B. Holmqvist, George R. Lynch, John H. Edmondson 2012-03-06 $13,200,000
8108610 Cache-based control of atomic operations in conjunction with an external ALU block David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2012-01-31 $9,973,000
8099650 L2 ECC implementation David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra 2012-01-17 $16,952,000
8060700 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, John H. Edmondson 2011-11-15 $13,698,000
7024545 Hybrid branch prediction device with two levels of branch prediction cache Gerald D. Zuraski, Jr. 2006-04-04 $14,413,000
6502188 Dynamic classification of conditional branches in global history branch prediction Gerald D. Zuraski, Jr., Raghuram S. Tupuri 2002-12-31 $2,157,000
6427192 Method and apparatus for caching victimized branch predictions 2002-07-30 $3,277,000
6393536 Load/store unit employing last-in-buffer indication for rapid load-hit-store William A. Hughes 2002-05-21 $2,063,000
6279106 Method for reducing branch target storage by calculating direct branch targets on the fly 2001-08-21 $5,111,000