Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515011 | Compression status bit cache and backing store | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2019-12-24 |
| 9639466 | Control mechanism for fine-tuned cache to backing-store synchronization | James Robertson, Gregory MUTHLER, Hemayet Hossain, Timothy John Purcell, Karan Mehra +1 more | 2017-05-02 |
| 9110809 | Reducing memory traffic in DRAM ECC mode | Karan Mehra, George R. Lynch, James Robertson, Gregory MUTHLER, Wishwesh Anil Gandhi +1 more | 2015-08-18 |
| 8949541 | Techniques for evicting dirty data from a cache using a notification sorter and count thresholds | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts, John H. Edmondson | 2015-02-03 |
| 8874844 | Padding buffer requests to avoid reads of invalid data | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts | 2014-10-28 |
| 8868838 | Multi-class data cache policies | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts | 2014-10-21 |
| 8862823 | Compression status caching | David B. Glasco, Cass W. Everitt, David Kirk McAllister, Emmett M. Kilgariff, George R. Lynch +4 more | 2014-10-14 |
| 8700862 | Compression status bit cache and backing store | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2014-04-15 |
| 8627041 | Efficient line and page organization for compression status bit caching | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts +2 more | 2014-01-07 |
| 8595437 | Compression status bit cache with deterministic isochronous latency | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2013-11-26 |
| 8504773 | Storing dynamically sized buffers within a cache | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts | 2013-08-06 |
| 8464001 | Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism | John H. Edmondson, David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts | 2013-06-11 |
| 8319783 | Index-based zero-bandwidth clears | David Kirk McAllister, Steven E. Molnar, Jerome F. Duluk, Jr., Cass W. Everitt, Emmett M. Kilgariff +2 more | 2012-11-27 |
| 8271734 | Method and system for converting data formats using a shared cache coupled between clients and an external memory | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-09-18 |
| 8244984 | System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts, John H. Edmondson | 2012-08-14 |
| 8234478 | Using a data cache array as a DRAM load/store buffer | James Roberts, David B. Glasco, Patrick R. Marchand, George R. Lynch, John H. Edmondson | 2012-07-31 |
| 8156404 | L2 ECC implementation | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-04-10 |
| 8135926 | Cache-based control of atomic operations in conjunction with an external ALU block | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-03-13 |
| 8131931 | Configurable cache occupancy policy | James Roberts, David B. Glasco, Patrick R. Marchand, George R. Lynch, John H. Edmondson | 2012-03-06 |
| 8125489 | Processing pipeline with latency bypass | Robert J. Stoll, John A. Schachte | 2012-02-28 |
| 8108610 | Cache-based control of atomic operations in conjunction with an external ALU block | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-01-31 |
| 8099650 | L2 ECC implementation | David B. Glasco, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-01-17 |
| 8060700 | System, method and frame buffer logic for evicting dirty data from a cache using counters and data types | David B. Glasco, George R. Lynch, Patrick R. Marchand, James Roberts, John H. Edmondson | 2011-11-15 |
| 7868901 | Method and system for reducing memory bandwidth requirements in an anti-aliasing operation | John H. Edmondson, Steven E. Molnar, Bengt-Olaf Schneider, Gary C. King, Michael J. M. Toksvig +1 more | 2011-01-11 |
| 7791611 | Asynchronous reorder buffer | Robert J. Stoll | 2010-09-07 |