Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Cache memory subsystem including a fixed latency R/W pipeline

Cache memory subsystem including a fixed latency R/W pipeline

US Patent 7251710 · Granted Jul 31, 2007

Estimated economic value: $9,995,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Speculatively executing instructions that follow a status updating instruction2023
Charging ports with integrated contactless communication units2022
Contactless communication interface systems and methods2022
System, method and apparatus for executing instructions2022
Executing a set of load operations for a gather-load instruction and controlling2022
Apparatus and method for operating an issue queue2022
Data processing2022
Correlated addresses and prefetching2022
Cache content management2022
Operation cache compression2022
Cache retention data management2021
Multi-protocol contactless communication2021