Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10176104 | Instruction predecoding | Vasu Kudaravalli, Matthew Paul Elwood, Adam George, Muhammad Umar Farooq | 2019-01-08 |
| 10140216 | Measuring address translation latency | Michael John Williams, Hazim Shafi | 2018-11-27 |
| 10102143 | Eviction control for an address translation cache | Barry Duane Williamson, Abhishek Raja, Adrian Montero, Miles Robert Dooley | 2018-10-16 |
| 9996471 | Cache with compressed data and tag | Ali Ghassan Saidi, Kshitij Sudan, Andrew Joseph RUSHING, Andreas Hansson | 2018-06-12 |
| 9600179 | Access suppression in a memory device | Yew Keong Chong, Gus Yeung, Andy Wangkun Chen, Sriram Thyagarajan | 2017-03-21 |
| 9542194 | Speculative register file read suppression | Chris Abernathy, Florent Begon | 2017-01-10 |
| 9477600 | Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode | Jamshed Jalal, Mark David Werkheiser, Brett S. Feero | 2016-10-25 |
| 9411362 | Storage circuitry and method for propagating data values across a clock boundary | Brett S. Feero | 2016-08-09 |
| 8949547 | Coherency controller and method for data hazard handling for copending data access requests | Phanindra Kumar Mannava, Jamshed Jalal, Ramamoorthy Guru Prasadh | 2015-02-03 |
| 8935485 | Snoop filter and non-inclusive shared cache memory | Jamshed Jalal, Brett S. Feero, Mark David Werkheiser | 2015-01-13 |
| 8490107 | Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels | Jamshed Jalal, Mark David Werkheiser, Brett S. Feero, Ramamoorthy Guru Prasadh, Phanindra Kumar Mannava | 2013-07-16 |
| 8463958 | Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices | Phanindra Kumar Mannava, Jamshed Jalal, Ramamoorthy Guru Prasadh, Bruce James Mathewson, Timothy Charles Mace | 2013-06-11 |
| 8463960 | Synchronisation of data processing systems | Phanindra Kumar Mannava, Jamshed Jalal, Ramamoorthy Guru Prasadh | 2013-06-11 |
| 7836259 | Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy | James K. Pickett, Roger D. Isaac | 2010-11-16 |
| 7415597 | Processor with dependence mechanism to predict whether a load is dependent on older store | James K. Pickett | 2008-08-19 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor | Arun Radhakrishnan, Benjamin T. Sander, Michael T. Clark, David E. Kroesche | 2008-05-13 |
| 7363470 | System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor | James K. Pickett, Benjamin T. Sander | 2008-04-22 |
| 7321964 | Store-to-load forwarding buffer using indexed lookup | James K. Pickett | 2008-01-22 |
| 7266673 | Speculation pointers to identify data-speculative operations in microprocessor | James K. Pickett, Benjamin T. Sander | 2007-09-04 |
| 7251710 | Cache memory subsystem including a fixed latency R/W pipeline | Roger D. Isaac, Mitchell Alsup, Rama S. Gopal, James K. Pickett | 2007-07-31 |
| 7165167 | Load store unit with replay mechanism | James K. Pickett, Benjamin T. Sander, Rama S. Gopal | 2007-01-16 |
| 7133969 | System and method for handling exceptional instructions in a trace cache based processor | Mitchell Alsup, Gregory W. Smaus, James K. Pickett, Brian D. McMinn, Benjamin T. Sander | 2006-11-07 |
| 6983389 | Clock control of functional units in an integrated circuit based on monitoring unit signals to predict inactivity | — | 2006-01-03 |
| 6976182 | Apparatus and method for decreasing power consumption in an integrated circuit | — | 2005-12-13 |
| 6950925 | Scheduler for use in a microprocessor that supports data-speculative execution | Benjamin T. Sander, Mitchell Alsup | 2005-09-27 |