Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10591977 | Segregated power state control in a distributed cache system | Mark David Werkheiser, Dominic William Brown, Ashley John Crawford | 2020-03-17 |
| 10423466 | Optimized streaming in an un-ordered interconnect | Ashok Kumar Tummala, Jamshed Jalal, Dimitrios Kaseridis | 2019-09-24 |
| 10402349 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, David Joseph Hawkins, Phanindra Kumar Mannava +1 more | 2019-09-03 |
| 10324858 | Access control | Bruce James Mathewson, Phanindra Kumar Mannava, Matthew Evans, Andrew Brookfield Swaine | 2019-06-18 |
| 10095631 | System address map for hashing within a chip and between chips | Gurunath Ramagiri | 2018-10-09 |
| 9891976 | Error detection circuitry for use with memory | Andy Wangkun Chen, Mudit Bhargava, Vikas Chandra | 2018-02-13 |
| 8977837 | Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes | Robert Gregory McDonald | 2015-03-10 |
| 8725953 | Local cache power control within a multiprocessor system | Nigel C. Paver, Stuart David Biles, Kevin Welton | 2014-05-13 |
| 8255629 | Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers | David Williamson, Simon John Craske | 2012-08-28 |
| 7047271 | DSP execution unit for efficient alternate modes for processing multiple data sizes | Bradley C. Aldrich, Jose Fridman, Gang Liang | 2006-05-16 |
| 6725360 | Selectively processing different size data in multiplier and ALU paths in parallel | Bradley C. Aldrich, Jose Fridman, Gang Liang | 2004-04-20 |
| 5889975 | Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core | Stephen Strazdus, Dennis M. O'Connor, Thomas Adelmeyer, Jay Heeb, Avery C. Topps | 1999-03-30 |